Display LVDS/MIPI D-PHY/sub-LVDS combo Transmitter 1.0G/2.5G/1.0Gbps 10-Lane

Overview

Key Features

• Support Mode: LVDS, sub-LVDS, D-PHY
• Data Rate: Up to 1.0 Gbps for LVDS, subLVDS / 2.5Gbps for DPHY
• Clock polarity programmable
• Data polarity for each data lane is programmable
• Integrated Integer-N PLL
• 4 programable level of output differential voltage
• BIST function for loopback test
• Operational modes supported:
  • - to support LVDS dual link (5 data lanes + 1 clock lane) x 2 channel
  • - to support subLVDS link (5 data lanes + 1 clock lane) x 2 channel
  • - to support DPHY TX @ 2.5Gbps (4 data lanes + 1 clock lane)

Benefits

• This IP has three operating modes and supports connection to a variety of displays.
• By developing an SOC equipped with this IP, customers can select the optimal interface from three interface types by changing the internal settings.
• This increases the flexibility of connected displays.
• In addition, LVDS mode allows amplitude adjustment when using long cables, increasing the flexibility of the connection environment.
• We can also supply link controllers that are compatible with this combo PHY.
• This IP can be implemented in a lane units and can be tailored to meet customer specifications.

Applications

• Display Application
  • Automotive
  • Navigation system
  • DSC(Digital Still Camera)

Deliverables

• Verilog Model (verilog / vcs)
• .db file / .lib(Option) file
• symbol / LVS netlist / Hspice netlist(Option)
• LEF, layer map file, layout technology file
• Layout Verification Report (DRC & LVS), Command file
• Datasheet
• Packaging and Layout Guideline / PCB Guideline
• Static Delay Analysis (STA) Guideline
• Testing Guideline (Option)
• RX Verilog Model and Test Vector(Option)
• Combo Link Layer IP(CD12661IP) and FPGA Board(Option)

Technical Specifications