The 32-bit A27 is a 5-stage processor that supports the latest RISC-V specification, including "G" ("IMAFD") standard instructions, "C" 16-bit compression instructions, "P" Packed-SIMD/DSP instructions, "N" for user-level interrupts, and Memory Management Unit (MMU) for Linux support.
A27 features branch prediction, instruction and data caches, local memories, ECC error protection, and Andes Custom Extension™ to add custom instructions to accelerate performance and reduce power consumption. In addition, it incorporates MemBoost to greatly enhance memory bandwidth and reduce memory latencies for applications with intensive memory accesses. A27 also includes vectored and preemptive interrupt controller to serve diversified system events, AXI 64-bit bus, rich power management, and JTAG debug interface and trace interface for software development support.
Compact High-Speed 32-bit CPU Core with MemBoost and PMA
Overview
Key Features
- AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
- Floating point extensions
- DSP/SIMD ISA to boost the performance of voice, audio, image and signal processing
- Andes extensions, architected for performance and functionality enhancements
- Separately licensable Andes Custom Extension™ (ACE) for customized acceleration
- 32-bit, 5-stage pipeline CPU architecture
- 16/32-bit mixable instruction format for compacting code density
- Branch predication to speed up control code
- Return Address Stack (RAS) to speed up procedure returns
- Memory Management Unit (MMU), Physical Memory Protection (PMP) and Programmable Physical Memory Attributes (PMA)
- MemBoost for heavy memory transactions
- Flexibly configurable Platform-Level Interrupt Controller (PLIC) for supporting wide range of system event scenarios
- Enhancement of vectored interrupt handling for real-time performance
- Advanced CoDense™ technology to further reduce code size on top of "C" extension
Block Diagram
Applications
- Machine/Deep Learning acceleration
- Networking and Communications
- Video and Image Processing
- Advanced Storage Device Control
Technical Specifications
Related IPs
- Compact High-Speed 32-bit CPU Core with DSP
- Compact High-Speed 32-bit CPU Core with Level-2 Cache
- Compact High-Speed 32-bit CPU for Real-time and Linux Applications
- Compact High-Speed 32-bit CPU Core
- 64-bit CPU with Modern RISC Architecture, MemBoost and PMA
- Compact High-Speed 64-bit CPU for Real-time and Linux Applications