eMMC Verification IP

Overview

eMMC Verification IP is an advanced solution in the market for the verification of eMMC implementations. It is adherent with eMMC standard JESD84-A441, JESD84-B45, JESD84-B50, JESD84-B51, JESD84-B51A & eMMC 5.2(Draft). It can generate all command types. The eMMC VIP monitor acts as powerful protocol-checker, fully compliant with eMMC JESD84-B51 specification.

eMMC JESD84-A441, JESD84-B45, JESD84-B50, JESD84-B51, JESD84-B51A and eMMC 5.2(Draft) includes extensive test suite covering most of the possible scenarios and eMMC conformance norms. eMMC JESD84-A441, JESD84-B45, JESD84-B50, JESD84-B51, JESD84-B51A & eMMC 5.2(Draft) VIP can perform all protocol tests as testbench and moreover it allows an easy generation of a very high number of patterns and a set of specified patterns to stress the DUT.

eMMC Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

eMMC Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

  • Supports eMMC standard JESD84-A441, JESD84-B45, JESD84-B50, JESD84-B51 and JESD84-B51A specification.
  • Supports stream transfer operations.
  • Supports three different data width bus modes
    • 1-bit(default)
    • 4-bit
    • 8-bit
  • Supports boot operation mode with simple boot sequence method.
  • Supports alternative boot operation mode.
  • Supports higher than 2GB of density of memories.
  • Supports hardware reset signal.
  • Supports high speed boot operation.
  • Supports command queuing.
  • Supports enhanced strobe.
  • Supports extended security protocols commands.
  • Supports production state awareness.
  • Supports secure write protect mode.
  • Supports Replay Protected Memory Block(RPMB) functionality.
  • Supports Single byte, single block, multiple block (finite and infinite) transfers and MMC stream transfer operations.
  • Supports send tuning block(CMD21) command.
  • Supports HS200 and HS400 Mode.
  • Supports data protection mechanism like password, permanent ,power-on and temporary.
  • Supports data removable mechanism.
  • Supports packed commands.
  • Supports high voltage & dual voltage.
  • Supports single data rate & dual data rate.
  • Supports write protection features for the boot and user areas, which may be permanent, power-on or temporary.
  • Tracking of transmit and receive counters.
  • Supports bus accurate timing.
  • Detects and reports the following errors.
    • Out of range error
    • Address misalign error
    • CRC error
    • Switch error
    • Illegal command error
    • Block length error
    • Lock-unlock failed error
    • Erase sequence error
    • Direction bit error
    • Stuff bit error
    • Erase param error
    • Reserved bit error
    • WP violation error
    • CSD/CID over write error
  • Protocol Checker fully compliant with eMMC JESD84-A441, JESD84-B45, JESD84-B50, JESD84-B51 and JESD84-B51A Specification.
  • Functional coverage for complete JESD84-A441, JESD84-B45, JESD84-B50, JESD84-B51 and JESD84-B51A.
  • Supports constraints randomization.
  • eMMC Verification IP comes with complete testsuite to test every feature of JESD84-A441, JESD84-B45, JESD84-B50, JESD84-B51 and JESD84-B51A.
  • Configurable as agent (frame generator) or monitor.
  • Status counters for various events on bus.
  • Monitors, detects and notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.

Benefits

  • Faster testbench development and more complete verification of eMMC designs.
  • Simplifies results analysis.
  • Easy to use command interface simplifies testbench control and configuration of slave and host.
  • Runs in every major simulation environment.

Block Diagram

eMMC Verification IP Block Diagram

Deliverables

  • Complete regression suite containing all the eMMC testcases.
  • Examples showing how to connect various components, and usage of Host, Slave and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation contains User's Guide and Release notes.

Technical Specifications

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