Comprehensive memory model and PHY verification
HBM VIP is a comprehensive memory VIP solution portfolio for high bandwidth memory (HBM), targeting a new standard in memory performance, density, power consumption, and cost. HBM VIP is intended for SoC and memory control ler designers who employ external HBM modules and PHY developers to ensure both comprehensive verification and protocol and timing compliance. Using a truly flexible and open architecture based on a 100% native SystemVerilog and UVM implementation, Avery HBM VIP implements a complete set of models and timing and protocol checkers.