The CAN Controller implements a Controller Area Network as specified in the ISO 11898 Part 1 and in the CAN Specification Version 2.0.
The Controller Area Network (CAN) is a serial communications protocol which efficiently supports distributed real-time control with a very high level of security.
Its domain of application ranges from high speed networks to low cost multiplex wiring. In automotive electronics, engine control units, sensors, anti-skid-systems, etc. are connected using CAN with bit rates up to 1 Mbit/s. At the same time it is cost effective to build into vehicle body electronics, e.g. lamp clusters, electric windows etc. to replace the wiring harness otherwise required.
The CAN Controller has been developed to DAL A according to the DO-254 / ED-80 and is accompanied by a Certification Kit. For lower DAL levels reduced documentation sets are available. The core is also available as a netlist for DAL D or projects not needing the full RTL source.
The CAN Controller is already being used in two programs: a civil rotorcraft and a civil large airplane, both as DAL A.
Implementation Details
The following tables show some examples of implementing the CAN Controller in different technologies and devices. Note that the CAN Controller is technology independent, and therefore it can be implemented in any technology/device as long as it contains enough resources (Flip-Flops, gates, pins, etc.).
Unless otherwise specified all the runs have been performed with the default options of the respective tool. Register placement on the IO has been disabled.
No constraints were added, so the results listed under the column “Maximum ‘clk’ Frequency” are the worst case scenario (no multicycle, false paths, etc. defined).
The results are provided for a CAN Core with TTC counters of 16 bits (‘g_TTC_COUNTER_SIZE’ = 16) and without TMR (Triple Module Redundancy). If TMR is used the number of registers will be triplicated, the combinatorial logic will also increase and there might be a penalty on the Maximum ‘clk’ Frequency.
ACTEL / MICROSEMI
| FPGA Type | Maximum ‘clk‘ Frequency | Logic Modules (CORE) |
|---|---|---|
| ProASIC3
(A3P1000 484FBGA I Std) |
53.5 MHz | 2604 |
| IGLOO
(AGL1000V5 484FBGA I Std) |
50.49 MHz | 2604 |
| Fusion
(AFS1500 676FBGA I Std) |
53.47 MHz | 2637 |
| Axcelerator
(RTAX1000S 352CQFP Mil Std) |
66.35 MHz | SEQUENTIAL (R-cells): 663
COMB (C-cells): 1432 |
ALTERA
| FPGA Type | Maximum ‘clk’ Frequency | Flip-Flops | ALUTs | ALMs | Logic Cells |
|---|---|---|---|---|---|
| MAX II
(EPM2210FF324I5) |
59.59 MHz | 610 | – | – | 1394 |
| Cyclone III
(EP3C16F484I7) |
120 MHz | 610 | – | – | 1303 |
| Stratix II
(EP2S60F484I4) |
173 MHz | 610 | 783 | 566 | – |
| Stratix III
(EP3SE110F780I3) |
> 220 MHz | 610 | 779 | 548 | – |
| Stratix IV
(EP4SGX70HF35C2) |
> 240 MHz | 610 | 797 | 547 | – |
XILINX
| FPGA Type | Maximum ‘clk‘ Frequency | Flip-Flops | 4-LUTs | Slices | Macrocells |
|---|---|---|---|---|---|
| CoolRunnerII
(XC2C128-6-TQ144) |
NA | NA | – | – | NA |
| Spartan3
(XC3S1000-5FG456) |
104 MHz | 617 | 1377 | 846 | – |
| Virtex2
(XC2V1000-6BG575) |
128 MHz | 616 | 1344 | 825 | – |
| Virtex4
(XC4VLX15-12SF36 |
182 MHz | 615 | 1384 | 847 | – |
| Virtex5
(XC5VLX30-3FF676) |
234 MHz | 564 | – | 430 | – |
