The Distributed Memory Generator is provided under the terms of the Xilinx End User License and is included with ISE® and Vivado™ design tools at no additional charge.
The Distributed Memory Generator IP core creates a variety of memory structures using Select RAM. It can be used to create Read Only Memory (ROM), single-port Random Access Memory (RAM), and simple dual/Dual port RAM as well as SRL16-based RAM. Flexible feature set allows users to customize for Memory type, Data width, Memory size, Input/Output options and reset options.
Distributed Memory Generator
Overview
Key Features
- Generates Read Only Memories (ROMs), Single, Simple Dual and Dual-port Random Access Memories (RAMs), and SRL16-based RAMs
- Supports data depths ranging from 16 to 65,536 words
- Supports data widths ranging from 1 to 1024 bits
- Optional registered inputs and outputs
- Example Design helps you get up and running quickly
Technical Specifications
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