B65LLDDRPHY-D3LP23 IP is compliant to JESD79-3F(DDR3), JESD209-2F(LPDDR2), JESD209-3B(LPDDR3),DFI3.1 specification and delivers an unbeatable combination of DDR speed and low power operation. With DSCL and DABC technology, B65LLDDRPHY-D3LP23 IP can automatically compensate chip/package/board/memory PVT variation and bit-bit skew. B65LLDDRPHY-D3LP23 delivers the highest DDR performance, the smallest area and the shortest bring up time.
It is easy to integrate B65LLDDRPHY-D3LP23 with BDDRCTL-D3LP23 controller IP or other third party DDR controller through the AHB/APB register interface and DFI3.1 interface. Technique support will be provided to help the customer for integration/validation.
DDR3/LPDDR23 PHY - 65LL
Overview
Key Features
- Max data rate 1600Mbps
- Comprehensive DDR3/LPDDR23 training
- CA training
- DQ read training
- DQ write training
- Write leveling
- PHY is DFI 3.1 compatible and backwards-compatible to earlier DFI standards for simplified integration with existing DFI-compliant Controllers
- PHY includes DSCL technology
- Automatically compensates for DDR interface timing due to static (process-related) variations and dynamic variations due to operating temperature, voltage, and data patterns
- PHY includes DABC technology
- Automatically compensates for bit-bit skew within each byte lane
- Flexible, rectilinear PHY layout offers industry’s smallest PHY area and is hardened to match IO pad frame
- DSCL delivers lowest PHY latency of 0.5 – 1 clock cycles
- PHY (and optionally IO) configured as drop-in hard macro for easy implementation
- Fast and simple system bring-up via DSCL hardware routine
- Improved long term system reliability
Deliverables
- Technical reference manual
- Encrypted Verilog simulation model (ncverilog/vcs)
- .db, .lib, .vg, .lef, .gdsII, .spef, .sdf
- Timing report
Technical Specifications
Foundry, Node
65LL
Availability
Developing