Gigacom's VSL320 PHY is a member of the Velocity™ Serial Link family of high-speed interface solutions. The VSL PHY family addresses many existing and emerging interface standards with scalable and silicon-efficient products. This comprehensive family of products covers a wide range of standards from 1.06 Gbps to 6.4 Gbps with the smallest footprints in the industry. The benefits of these highly integrated PHY solutions include differentiated performance, simplified interoperability and extensive built-in testability. Gigacom minimizes risk with our silicon verification/interoperability program, resulting in highly reliable products which are manufacturable in leading CMOS processes.
XAUI PHY
Overview
Key Features
- Very low output jitter
- Receiver equalization for enhanced jitter tolerance
- Programmable TX levels with multiple post-cursor emphasis options
- Automatic driver/receiver impedance calibration
- 8/10 bit interface or 16/20 bit interface
- Signal detection
- Power saving modes
- Status pins for checking PHY functionality
- Integrated bandgap
- Extensive built in testability
- At-speed BIST circuitry with various PRBS and 8B10B patterns
- Multiplexed scan for testability of all digital logic
- Eye width mapping and on chip jitter generation capability
- Loop back modes
- Serial Control Register
- Support for DC and AC JTAG (AC EXTEST)
Benefits
- Low Risk - Silicon proven today in multiple foundries and processes with Extensive Si characterization data
- Excellent Interoperability - LC tank oscillator that gives low noise and jitter
- Superior Noise Immunity - Fully differential circuitry and Voltage Regulator for enhanced noise immunity
- Low Power - As low as 60mW per lane at 3.125Gb/s
- Minimal Area - for Wire bond as well as flip-chip package
- Improve Test Coverage - Multiple loopback modes with 12 built-in patterns
- Scan built in to all digital,Serial Control Register (SCR) for simplified testing, JTAG support (DC and AC )
- Lowest Total Cost of Ownership
- Customization/ Integration support
Block Diagram
Applications
- Chip-to-chip communications in:
- Networking/ Communications
- Data Processing
- Industrial/ Others
Deliverables
- Abstract LEF
- Behavioral Model Verilog
- Timing Model .LIB
- High-speed IO Model hSpice
- LVS Netlist CDL
- Physical database GDSII
- Documentation pdf
Technical Specifications
Foundry, Node
TSMC 65nm GP, TSMC 65nm LP, Global foundries 65nm LP, Global foundries 40nm LP, Silicon proven in TSMC 28nm HPC/HPC+
Maturity
In production
Availability
Immediately
GLOBALFOUNDRIES
Pre-Silicon:
40nm
LP