DDR2/MDDR COMBO PHY Data block for Chip usage ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process
Overview
DDR2/MDDR COMBO PHY Data block for Chip usage ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process
Technical Specifications
Foundry, Node
UMC 55nm
Maturity
Pre-Silicon release
UMC
Pre-Silicon:
55nm
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