DDR DLL (All Digital) IP, Input: 800MHz - 1600MHz, Output: 800MHz - 1600MHz, UMC 28nm HPM process
Overview
Input 800M-1600MHz, output 800M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in period of FREF, UMC 28nm Logic and Mixed-Mode HPM process.
Technical Specifications
Foundry, Node
UMC 28nm HPM
UMC
Pre-Silicon:
28nm
HPM
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