DCD's Universal Timers System

Overview

The DUTS stands for DCD’s Universal Timers System. It is a programmable and highly configurable device that comprises seven submodules:
Pulse Width Modulation (PWM)
Timer 1
Timer 2
Timer 3
Real-Time Interrupt (RTI)
Computer Operates Properly (COP)
Pulse Accumulator (PA)

Each of these standalone modules provides useful functionalities which enable many design possibilities. Furthermore, if some module is not being used, it is possible to exclude it from design via one parameter. Moreover, in the case of the Timer 1 submodule, it is possible to exclude single Output-Compare or Input-Capture function logic when it is not used. This enables the minimization of hardware resources utilization. Moreover, users can switch between 8-bit and 32-bit DUTS native interfaces.

Key Features

  • PWM:
    • Up to Four 8-bit pulse widths or concatenated two 16-bits modulated waveforms
    • Three software-selectable clock sources
    • Software selectable polarity of the output waveform
    • Double buffered period and duty cycle registers for each PWM channel
  • Timer 1:
    • Free running 16-bit counter with a 4-stage programmable prescaler
    • Timer overflow function
    • Up to four independent, configurable Input Capture functions
    • Up to five Output Compare, configurable functions
    • Interrupt controls and separate interrupt vectors of each IC, OC, and timer overflow
  • Timer 2:
    • 16-bit counter with a 4-stage programmable prescaler
    • Up to four Output Compare functions
    • One Input Capture function
    • Event counting mode
    • Possibility to stop the counter
    • Timer overflow function
    • Interrupt controls and interrupt vectors of IC, OC, and timer overflow
  • Timer 3:
    • 16-bit counter with a 3-stage programmable prescaler or with Timer 1 clock rate
    • Up to four Output Compare functions
    • One Input Capture function
    • Event counting mode
    • Possibility to stop the counter
    • Timer overflow function
    • Interrupt controls and interrupt vectors of IC/OC and timer overflow
  • Real-Time Interrupt:
    • Hardware interrupts at a fixed periodic rate
    • Four different interrupt rates
    • Constant RTI timeouts
  • Computer Operates Properly:
    • Configurable clock source
    • Scaling of watchdog overflow time
    • Protection from software malfunctions
  • Pulse Accumulator:
    • 8-bit counter
    • Event counter mode and gated time accumulation mode
    • Maskable interrupts
  • Fully synthesizable
  • No internal tri-states
  • Available system interface wrappers:
    • Native 8-bit interface
    • Native 32-bit interface
    • AMBA – APB / AHB / AXI Lite Bus
  • Configurable reset
  • Configurable interface control pins activity level
  • Simple internal structure configuration

Benefits

  • Rapid prototyping and time-to-market reduction
  • Design risk elimination
  • Development costs reduction
  • Full customization
  • Global sales network
  • Technology independence
  • Professional service
  • Getting a sillicon proven IP

Applications

  • Serial Data communications applications
  • Modem interface
  • Embedded microprocessor boards

Deliverables

  • HDL Source Code
  • Testbench environment
    • Automatic Simulation macros
    • Tests with reference responses
  • Synthesis scripts
  • Technical documentation
  • 12 months of technical support

Technical Specifications

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