Vendor: Logic Design Solutions Category: UART

Universal Asynchronous Receiver / Transmitter

The macro M16550, implements a synchronous universal asynchronous receiver/transmitter, which provides an interface between a mic…

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Overview

The macro M16550, implements a synchronous universal asynchronous receiver/transmitter, which provides an interface between a microprocessor and a serial communication channel.
This macro can be customized according to specific needs (application-specific requirement). Any other pre-designed functions can be integrated into the FPGA. FPGA density and I/O requirements can be defined according to customer specification.

Key features

  • Single-chip synchronous UART
  • Functionally based on the National Semiconductor Corporation NS16550 device
  • Designed to be included in high-speed and high-performance applications
  • System clock up to 150 MHz
  • CPU independent interface
  • Complete asynchronous communication protocol including :
    • 5,6,7 or 8-bit data transmission
    • Even/Odd or no parity bit generation and detection
    • Start and Stop bit generation and detection
    • Line break generation and detection
    • Receiver Overrun and framing detection
  • Up to 1M baud (system frequency dependent)
  • 1 to 65535 divisor generates 16X clock
  • Buffered transmit and receive registers
  • Transmitter and receiver are buffered with 16 Byte FIFO, plus 3 error bits per data byte on receiver
  • Polled or interrupt mode
  • Loopback mode

What’s Included?

  • VHDL Source code
  • VHDL Test Bench for behavioural and gate level simulation.
  • Data Sheet and Reference Guide
  • User’s guide : Simulation, Synthesis and Place and Route procedures.
  • Constraint File

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
M16550
Vendor
Logic Design Solutions
Type
Silicon IP

Provider

Logic Design Solutions
HQ: FRANCE
Logic Design Solutions is an FPGA Design and Intellectual Property (IP) company that provides Design Services, IP (cores) and DO254 methodology to FPGA customers. We engage ourself to be your high standard quality solutions provider for FPGA cores and Design Services.
Contact Logic Design Solutions

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Frequently asked questions about UART IP cores

What is Universal Asynchronous Receiver / Transmitter?

Universal Asynchronous Receiver / Transmitter is a UART IP core from Logic Design Solutions listed on Semi IP Hub.

How should engineers evaluate this UART?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this UART IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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