CRAM Memory Model

Overview

CRAM Memory Model provides an smart way to verify the CRAM component of a SOC or a ASIC. The SmartDV's CRAM memory model is fully compliant with standard CRAM Specification and provides the following features. Better than Denali Memory Models.

CRAM Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

CRAM Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Supports CRAM memory devices from all leading vendors.
Supports 100% of CRAM protocol standard.
Supports all the CRAM commands as per the specification.
Supports write cycles operation.
Supports read cycles operation.
Supports wrap or sequential burst order.
Supports for 4, 8, 16 and 32 Programmable burst lengths.
Supports following device types,
- X4
- X8
- X16
Checks for following
- Check-points include power on, Initialization and power off rules
- Read/Write Command rules etc.
- All timing violations
Supports below low power features
- On-chip temperature-compensated refresh
- Partial-array refresh mode
- Deep power-down mode
Supports full-timing as well as behavioral versions in one model.
Supports all timing delay ranges in one model: min, typical and max.
Protocol checker fully compliant with CRAM Specification.
Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
Constantly monitors CRAM behavior during simulation.
Built in functional coverage analysis.
Supports Callbacks, so that user can access the data observed by monitor.

Benefits

Faster testbench development and more complete verification of CRAM designs.
Easy to use command interface simplifies monitor control and configuration.
Simplifies results analysis.
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite containing all the CRAM testcases.
Complete UVM/OVM sequence library for CRAM controller.
Examples showing how to connect and usage of Model.
Detailed documentation of all class, task and function's used in verification env.
Documentation also contains User's Guide and Release notes.

Technical Specifications

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