Combined PROM/IO/SRAM/SDRAM Memory controller with EDAC

The FTMCTRL can handle four types of devices: PROM, asynchronous static ram (SRAM), synchronous dynamic ram (SDRAM) and memory mapped I/O devices (I/O). The PROM, SRAM and SDRAM areas can be EDAC-protected using a (39, 7) BCH code. The EDAC provides single error correction and double-error detection for each 32-bit memory word.

The core supports 8-/16- and 32-bit wide PROM,IO and SRAM memories/devices. The SDRAM can either be on the same memory bus as the other memories or on a separate bus. 32-bit wide memories are supported in the former case while the latter supports both 32/64-bits. EDAC for SDRAM is only supported for a 32-bit wide memory bus.

External chip-selects are provided for up to to four PROM banks, one I/O bank, five SRAM banks and two SDRAM banks.

Memory accesses are performed through an AHB slave interface while configuration registers are accessed through an APB interface.

The FTMCTRL is inherently portable and can be implemented on most FPGA and ASIC technologies.

The FTMCTRL core can be licensed under a commercial license as part of the GRLIB IP library.