HBM2/2E Memory Controller Core

The Rambus HBM2/2E Controller Core is designed for use in applications requiring high memory throughput, low latency and full programmability.

The core accepts commands using a simple local interface and translates them to the command sequences required by HBM2/2E devices. The core also performs all initialization, refresh and power-down functions.

The core queues up multiple commands in the command queue. This enables optimal bandwidth utilization for both short transfers to highly random address locations as well as longer transfers to contiguous address space. The command queue is also used to opportunistically perform look-ahead activates, precharges and auto-precharges, further
improving overall throughput.

The core supports all HBM2/2E features, including data bus inversion (DBI), DQ parity, command / address parity modes, and single-bank refresh. Add-On Cores such as a Multi-Port Front-End and Reorder Core can be optionally delivered with the core.

The core is delivered fully integrated and verified with the target HBM2/2E PHY.