AMBA APB Target
Overview
Advanced Peripheral Bus (APB) is one of the Advanced Microcontroller Bus Architecture (AMBA) family protocols. It is a low-cost interface that is designed for low power consumption and interface simplicity. Unlike AHB, it is a non-pipelined protocol for connecting low-bandwidth peripherals. Mostly used to link external peripherals to the SOC. Every APB transfer requires at least two clock cycles (SETUP Cycle and ACCESS Cycle) to finish. The APB interface is designed for accessing the programmable control registers of peripheral devices. The APB protocol has two independent data buses, one for read data and one for write data. The buses can be 8, 16, or 32 bits wide. The read and write data buses must have the same width. Data transfers cannot occur concurrently because the read data and write data buses do not have their own individual handshake signals.
Key Features
- Wait state
- Error reporting
- Transaction protection
- Sparse data transfer
- Flopped and non-flopped
- Synchronous or asynchronous reset type
- APB 4/ APB 2.0
Deliverables
- Agnisys provides a tool - IDesignSpec to configure the IP.
Technical Specifications
Maturity
Released
Availability
Now