The Roa Logic AHB-Lite Memory IP is a fully parameterized soft IP implementing on-chip memory for access by an AHB-Lite based Master. All signals defined in the AMBA 3 AHB-Lite v1.0 specifications are fully supported.
The IP supports a single AHB-Lite based host connection and enables address & data widths, memory depth & target technology to be specified via parameters. An option to register the memory output is also provided.
AHB-Lite General Purpose Memory Module
Overview
Key Features
- Full support for AMBA 3 AHB-Lite protocol
- Fully parameterized
- User-defined address and byte-aligned data widths supported
- Configurable memory depth, limited only by target technology capability
- Technology-specific memory cells instantiated automatically
- Combinatorial or registered data output
Benefits
- Design to support any silicon technology
Block Diagram
Deliverables
- Full Source Code
- Testbenches
- Compilation Scripts
- Documentation
Technical Specifications
Availability
Source Code Available Immediately