40LP PG SP-SRAM LVT Peripheral with Row redundancy for 213 cell
Overview
40LP PG SP-SRAM LVT Peripheral with Row redundancy for 213 cell
Technical Specifications
Foundry, Node
UMC 40nm Logic/Mixed_Mode LP
UMC
Pre-Silicon:
40nm
,
40nm
LP
Related IPs
- UMC 40nm Low Power Process PG SP-SRAM with Row redundancy for 213 bit cell
- 28nm HPM SP-SRAM with peri LVT row repair
- 28nm HPM SP-SRAM with peri LVT & row & 1 column repair
- UMC 40nm LP Logic Process standard synchronous high density dual port SRAM memory compiler with ROW redundancy with LVt peripheral
- UMC 40nm Low Power Process SP-SRAM memory compiler with row redundancy and 213 bit cell
- ISO/IEC 7816-3 digital controller for interface device compliant with ETSI TS 102 221 and EMV 2000 standards