The TRV101TSM40LP IP is a 1.1V low-power low-silicon-area 12-bit 80MHz Asynchronous-SAR ADC implemented in TSMC Low-Power 40nm CMOS process technology. Its 40MHz Nyquist bandwidth makes it especially suitable for use in carrier-aggregated wireless communication integrated circuit subsystems (LTE, WiFi, WiMAX etc).
12-bit 40nm 1.1V 80MHz Asynchronous-SAR ADC
Overview
Key Features
- Rail-to-Rail Input Capability
- Scalable Power Consumption
- No need for external high-speed SAR clock
- Internal Calibration Engine
- Selectable Two's Complement or Offset-binary data output
- 65dB SNR
Benefits
- Low-power and low-area fully-featured 12-bit ADC with rail-to-rail reference and integrated calibration engine and compensation logic.
Block Diagram
Applications
- ADC is suitable for embedding in ASIC and SoC subsystems for:
- LTE, WiFi, WiMAX and many more
Deliverables
- Behavioural Models
- Timing Models
- GDSII Layout Database
- Netlist for LVS verification
- Usage and Integration Guidelines
- Databook
Technical Specifications
Short description
12-bit 40nm 1.1V 80MHz Asynchronous-SAR ADC
Vendor
Vendor Name
Foundry, Node
TSMC 40nm CMOS
Maturity
Contact Tetrivis
Availability
GDSII available in January 2015
TSMC
Pre-Silicon:
40nm
LP
Related IPs
- 12-bit 40nm 1.1V 80MHz Asynchronous-SAR IQ ADC
- 12-bit 40nm 1.1V 64MHz-to-340MHz continuous-time Delta-Sigma ADC
- 40nm 1.1V AFE comprising 12-bit IQ ADC, 12-bit IQ DAC and Clock-PLL
- 12-bit 40nm 1.1V 320MHz Digitally-Assisted Current DAC
- 12-bit 40nm 1.1V 320MHz Digitally-Assisted IQ Current DAC
- 12-Bit 1MSPS SAR ADC, 10.5 Bit ENOB - SMIC 40nm