Quad-channel 12-bit 20 – 100 MSPS ADC contains four ADC channels, LVDS receiver, reference voltages and reference currents circuits. ADC employs a high-performance differential pipeline architecture. There are two operating mode with external and programmable internal references voltages. LVDS receiver supports rail to rail input range.
Quad-channel ADC requires: 1.08 ÷ 1.32 V analog supply and 1.08 ÷ 1.32 V digital supply.
LVDS receiver requires: 2.375 ÷ 2.625 V analog supply, 1.08 ÷ 1.32 V digital supply, differential input clock with duty cycle 45 ÷ 55 %.
Reference current block requires: reference current 9.9 ÷ 10.1 uA.
Reference voltages block requires external capacitors on pins «refp», «refz» and «refn».
Quad-channel ADC supports standby mode which allows state with minimum power consumption.
Each channel can be individually configured into operating mode. Parallel output is used.
The block is designed on TSMC CMOS 65 nm technology.
12-bit 4-channel 20 to 100 MSPS ADC
Overview
Key Features
- TSMC CMOS 65nm
- High speed pipelined ADC
- Resolution 12 bit
- Quad channel
- Conversion rate 20 – 100 MHz
- Different power supplies for digital (1.2 V) and analog (1.2 V) parts
- Low standby current 33 uA
- Low power dissipation 286.5 mW
- Spurious-free dynamic range 76.7 dB
- Signal-to-noise ratio 64 dB
- Compact die area 4.58 mm2
Applications
- Optical networking
- Test equipment
- Portable ultrasound and digital beam-forming systems
- Telecommunication systems
- High quality imaging video systems
- WiFi, WiMax
- Mobile Communications
- High quality imaging video systems
- Data acquisition systems
Deliverables
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
Technical Specifications
Foundry, Node
TSMC CMOS 65 nm
Maturity
Silicon proven
Availability
Now
TSMC
Pre-Silicon:
65nm
G
Silicon Proven: 65nm G
Silicon Proven: 65nm G