12-bit 1-channel 20 to 100 MSPS ADC

Overview

The low-power high-speed 12-bit ADC employs a high-performance differential pipeline architecture.
The ADC consists of a core ADC, output logic, timing generation, reference currents circuits. The ADC requires: 1.08 ÷ 1.32 V analog supply, 1.08 ÷ 1.32 V digital supply, differential reference voltages 0.85 V and 0.35 V, common mode voltage 0.6 V, reference current 9.9 ÷ 10.1 uA and differential input clock.
The ADC supports standby mode which allows state with minimum power consumption.
There is also the ability to configure the operating modes of the ADC by using digital registers.
The block is designed on TSMC CMOS 65 nm technology.

Key Features

TSMC CMOS 65nm
High speed pipelined ADC
Resolution 12 bit
Conversion rate 20 – 100 MHz
Different power supplies for digital (1.2 V) and analog (1.2 V) parts
Low standby current 33 uA
Low power dissipation 76.8 mW
Spurious-free dynamic range 76.7 dB
Signal-to-noise ratio 64 dB
Compact die area 1.03 mm2

Applications

Optical networking
Test equipment
Portable ultrasound and digital beam-forming systems
Telecommunication systems
High quality imaging video systems
WiFi, WiMax
Mobile Communications
High quality imaging video systems
 Data acquisition systems

Deliverables

Schematic or NetList
Abstract model (.lef and .lib files)
Layout view (optional)
Behavioral model (Verilog)
Extracted view (optional)
GDSII
DRC, LVS, antenna report
Test bench with saved configurations (optional)
Documentation

Technical Specifications

Foundry, Node

TSMC CMOS 65 nm

Maturity

Silicon proven

Availability

Now

TSMC

Silicon Proven: 65nm G

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