Mentor Graphics?A-XGFIF is a low gate count, easy-to-synthesize 10-Gbps FIFO module that offers increased system-level throughput by allowing data
queuing. The A-XGFIF module seamlessly integrates with Mentor's A-XGMAC 10-Gbps Ethernet MAC module.
The A-XGFIF is a feature-rich FIFO module including automatic pause-frame handshaking and support for per-frame-MAC-configuration overrides. Other
features of the A-XGFIF core include clock frequency independent I/O ports, single or multiple word I/O data transfers, full memory utilization with graceful
Receive memory-overflow recovery. The A-XGFIF module also provides programmable high and low Receive memory level indicators and pause-frame
handshaking reassertion intervals, high Transmit memory level indication, and CPU frame insertion and inspection capabilities.
10-Gigabit Ethernet FIFO Memory Interface
Overview
Key Features
- User-definable memory sizes
- Signal or multiple word transfers
- Programmable high and low receive memory level indicators
- Automatic pause frame handshaking
- Programmable high-transmit memory level indicator
- Graceful Rx memory overflow handling
- Tx memory under run indication
- Tx memory frame rewind capability
- Full utilization of synchronous dualport memories
- Optional per transmit frame MAC configuration support
Applications
- best suited for switches, multi-port bridges, and routers
Deliverables
- Verilog RTL source code
- Functional testbench
- Synthesis constraints files
- Module-level documentation
Technical Specifications
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