The DB-I2C-S-AXI-BRIDGE is an I2C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs not requiring internal configuration & control registers (and thus no local host CPU required), and an AXI Master interface for read/write to user system. The DB-I2C-S-AXI-BRIDGE processes the I2C protocol & physical layers, and receives & transmits bytes with respect to the I2C payload via the bridge AXI Master Interface to user registers or memory.
The DB-I2C-S-AXI-BRIDGE runs off the AXI Master external clock input within the ASIC / ASSP, providing a synchronous design while offering I2C spike filtering of SDA and SCL.
The DB-I2C-S-AXI-BRIDGE is a member of Digital Blocks DB-I2C Controller IP Core family, which includes I2C Master/Slave, I2C Master-only, and I2C Slave-only configurations.
Figure 1 depicts the DB-I2C-S-AXI-BRIDGE Core system view. The IP is configured by internal pre-synthesis parameters and post-synthesis top-level input signals, receives input clock and reset, and performs I2C Slave-Receiver transfers (for writing data to the AXI via its AXI Master Interface) and Slave-Transmitter transfers (for reading data from the AXI via the AXI Master Interface).
