The synthesizer produces stable clock signal in range from 1 to 600MHz. PLL with integer factors of the frequency division is used for synthesis.
External reference clock 6 MHz connects with pll_iclk input. The output of the frequency synthesizer forms a stable signal with a frequency from 1 to 600 MHz The range of possible frequencies is set by the dividing ratio control register pll_cfg<9:0> and output frequency is the register value in Mhz. The synthesizer is OFF if value register is 000h.
The device is designed with TSMC CMOS 90 nm technology.
1 – 600 MHz frequency synthesizer
Overview
Key Features
- TSMC CMOS 90 nm
- Reference frequency 6 MHz
- Output frequency 1 - 600 MHz
- Supply voltage 1 V
- Working supply current 1 mA
- Portable to other technologies (upon request)
Applications
- Data transmission systems
- Clock subsystems
- Measurement equipment
Deliverables
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
Technical Specifications
Foundry, Node
TSMC CMOS 90 nm
Maturity
Pre-verification
Availability
Now
TSMC
Silicon Proven:
90nm
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