Leveraging Virtual Platforms for Embedded Software Validation: Part 2
By Andy Ladd, Carbon Design Systems
Embedded.com (06/25/08, 04:16:00 PM EDT)
Embedded.com (06/25/08, 04:16:00 PM EDT)
Earlier in Part 1, we described the benefits of leveraging virtual platforms to validate architecture, performance and embedded software. In this second part, a case study is provided as a means to illustrate the concepts and benefits of using a well-modeled virtual platform of a simple system-on-chip (SoC) design.
The article will discuss how to effectively use interface and abstraction techniques, modeling tools, debugging techniques, and profiling to characterize and validate architectures and embedded software.
To read the full article, click here
Related Semiconductor IP
- Post-Quantum Digital Signature IP Core
- Compact Embedded RISC-V Processor
- Power-OK Monitor
- RISC-V-Based, Open Source AI Accelerator for the Edge
- Securyzr™ neo Core Platform
Related White Papers
- Leveraging virtual hardware platforms for embedded software validation
- Dealing with automotive software complexity with virtual prototyping - Part 3: Embedded software testing
- Processor-In-Loop Simulation: Embedded Software Verification & Validation In Model Based Development
- Fast virtual platforms open up multicore software development
Latest White Papers
- DRsam: Detection of Fault-Based Microarchitectural Side-Channel Attacks in RISC-V Using Statistical Preprocessing and Association Rule Mining
- ShuffleV: A Microarchitectural Defense Strategy against Electromagnetic Side-Channel Attacks in Microprocessors
- Practical Considerations of LDPC Decoder Design in Communications Systems
- A Direct Memory Access Controller (DMAC) for Irregular Data Transfers on RISC-V Linux Systems
- A logically correct SoC design isn’t an optimized design