Leveraging Virtual Platforms for Embedded Software Validation: Part 2
By Andy Ladd, Carbon Design Systems
Embedded.com (06/25/08, 04:16:00 PM EDT)
Earlier in Part 1, we described the benefits of leveraging virtual platforms to validate architecture, performance and embedded software. In this second part, a case study is provided as a means to illustrate the concepts and benefits of using a well-modeled virtual platform of a simple system-on-chip (SoC) design.
The article will discuss how to effectively use interface and abstraction techniques, modeling tools, debugging techniques, and profiling to characterize and validate architectures and embedded software.
Embedded.com (06/25/08, 04:16:00 PM EDT)
Earlier in Part 1, we described the benefits of leveraging virtual platforms to validate architecture, performance and embedded software. In this second part, a case study is provided as a means to illustrate the concepts and benefits of using a well-modeled virtual platform of a simple system-on-chip (SoC) design.
The article will discuss how to effectively use interface and abstraction techniques, modeling tools, debugging techniques, and profiling to characterize and validate architectures and embedded software.
To read the full article, click here
Related Semiconductor IP
- Multi-channel Ultra Ethernet TSS Transform Engine
- Configurable CPU tailored precisely to your needs
- Ultra high-performance low-power ADC
- HiFi iQ DSP
- CXL 4 Verification IP
Related Articles
- Leveraging virtual hardware platforms for embedded software validation
- Dealing with automotive software complexity with virtual prototyping - Part 3: Embedded software testing
- Processor-In-Loop Simulation: Embedded Software Verification & Validation In Model Based Development
- Fast virtual platforms open up multicore software development
Latest Articles
- GenAI for Systems: Recurring Challenges and Design Principles from Software to Silicon
- Creating a Frequency Plan for a System using a PLL
- RISCover: Automatic Discovery of User-exploitable Architectural Security Vulnerabilities in Closed-Source RISC-V CPUs
- MING: An Automated CNN-to-Edge MLIR HLS framework
- Fault Tolerant Design of IGZO-based Binary Search ADCs