Verification Platform for Complex Designs
By Amit Adua, Cadence Design Systems
December 31, 2007 -- edadesignline.com
Introduction
As the complexity of electronic designs continues to increase, the challenge of verifying their functional correctness is increasing as well. The problem is compounded with the increasing market demands to deliver the next more complex version of product in even lesser time and with tighter cost constraints. Under these circumstances, ensuring the functional correctness of the modern devices in given time can not be satisfactorily achieved by simply scaling up the verification resources using the traditional techniques. This makes it absolutely necessary for the companies that provide verification solutions ("the EDA verification companies") to deliver new products & techniques to do the verification tasks.
In this article the challenges faced in verifying today's complex designs are discussed. Along with, the corresponding advancements required in verification products and techniques to overcome these issues have been suggested. In a way, this article provides an insight of today's verification problems faced by semiconductor companies and also suggests what should be considered in the verification platforms to overcome these challenges.
December 31, 2007 -- edadesignline.com
Introduction
As the complexity of electronic designs continues to increase, the challenge of verifying their functional correctness is increasing as well. The problem is compounded with the increasing market demands to deliver the next more complex version of product in even lesser time and with tighter cost constraints. Under these circumstances, ensuring the functional correctness of the modern devices in given time can not be satisfactorily achieved by simply scaling up the verification resources using the traditional techniques. This makes it absolutely necessary for the companies that provide verification solutions ("the EDA verification companies") to deliver new products & techniques to do the verification tasks.
In this article the challenges faced in verifying today's complex designs are discussed. Along with, the corresponding advancements required in verification products and techniques to overcome these issues have been suggested. In a way, this article provides an insight of today's verification problems faced by semiconductor companies and also suggests what should be considered in the verification platforms to overcome these challenges.
To read the full article, click here
Related Semiconductor IP
- HBM4 PHY IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- HBM4 Controller IP
- IPSEC AES-256-GCM (Standalone IPsec)
- Parameterizable compact BCH codec
Related Articles
- Unique Approach to Verification of Complex SoC Designs
- FPGA based Complex System Designs: Methodology and Techniques
- Mixed Signal Design & Verification Methodology for Complex SoCs
- Dealing with memory access ordering in complex embedded designs
Latest Articles
- A 14ns-Latency 9Gb/s 0.44mm² 62pJ/b Short-Blocklength LDPC Decoder ASIC in 22FDX
- Pipeline Stage Resolved Timing Characterization of FPGA and ASIC Implementations of a RISC V Processor
- Lyra: A Hardware-Accelerated RISC-V Verification Framework with Generative Model-Based Processor Fuzzing
- Leveraging FPGAs for Homomorphic Matrix-Vector Multiplication in Oblivious Message Retrieval
- Extending and Accelerating Inner Product Masking with Fault Detection via Instruction Set Extension