Verification Platform for Complex Designs
December 31, 2007 -- edadesignline.com
Introduction
As the complexity of electronic designs continues to increase, the challenge of verifying their functional correctness is increasing as well. The problem is compounded with the increasing market demands to deliver the next more complex version of product in even lesser time and with tighter cost constraints. Under these circumstances, ensuring the functional correctness of the modern devices in given time can not be satisfactorily achieved by simply scaling up the verification resources using the traditional techniques. This makes it absolutely necessary for the companies that provide verification solutions ("the EDA verification companies") to deliver new products & techniques to do the verification tasks.
In this article the challenges faced in verifying today's complex designs are discussed. Along with, the corresponding advancements required in verification products and techniques to overcome these issues have been suggested. In a way, this article provides an insight of today's verification problems faced by semiconductor companies and also suggests what should be considered in the verification platforms to overcome these challenges.
To read the full article, click here
Related Semiconductor IP
- Flexible Pixel Processor Video IP
- Complex Digital Up Converter
- Bluetooth Low Energy 6.0 Digital IP
- Verification IP for Ultra Ethernet (UEC)
- MIPI SWI3S Manager Core IP
Related White Papers
- Unique Approach to Verification of Complex SoC Designs
- FPGA based Complex System Designs: Methodology and Techniques
- Mixed Signal Design & Verification Methodology for Complex SoCs
- Dealing with memory access ordering in complex embedded designs
Latest White Papers
- RISC-V basics: The truth about custom extensions
- Unlocking the Power of Digital Twins in ASICs with Adaptable eFPGA Hardware
- Security Enclave Architecture for Heterogeneous Security Primitives for Supply-Chain Attacks
- relOBI: A Reliable Low-latency Interconnect for Tightly-Coupled On-chip Communication
- Enabling Space-Grade AI/ML with RISC-V: A Fully European Stack for Autonomous Missions