TLM Peripheral Modeling for Platform-Driven ESL Design Using the SystemC Modeling Library
by Tim Kogel, CoWare Inc., Solution Specialist
Abstract
This article provides an overview of a SystemC-based Transaction Level Modeling (TLM) methodology for the rapid creation of SoC platform models. First a brief overview of the ESL design tasks and the corresponding modeling requirements is given. The main topic is a methodology for the efficient creation of transaction-level peripheral models. Those are usually specific for a particular SoC platform and have to be created by the ESL user.
Click here to access this paper (PDF file)
Related Semiconductor IP
- 8MHz / 40MHz Pierce Oscillator - X-FAB XT018-0.18µm
- UCIe RX Interface
- Very Low Latency BCH Codec
- 5G-NTN Modem IP for Satellite User Terminals
- 400G UDP/IP Hardware Protocol Stack
Related Articles
- SystemC: Key modeling concepts besides TLM to boost your simulation performance
- Using IP-XACT Metadata for a TLM Modeling Flow
- Open-Source Design of Heterogeneous SoCs for AI Acceleration: the PULP Platform Experience
- Unified Modeling in C++ & SystemC
Latest Articles
- SNAP-V: A RISC-V SoC with Configurable Neuromorphic Acceleration for Small-Scale Spiking Neural Networks
- An FPGA Implementation of Displacement Vector Search for Intra Pattern Copy in JPEG XS
- A Persistent-State Dataflow Accelerator for Memory-Bound Linear Attention Decode on FPGA
- VMXDOTP: A RISC-V Vector ISA Extension for Efficient Microscaling (MX) Format Acceleration
- PDF: PUF-based DNN Fingerprinting for Knowledge Distillation Traceability