TLM Peripheral Modeling for Platform-Driven ESL Design Using the SystemC Modeling Library
by Tim Kogel, CoWare Inc., Solution Specialist
Abstract
This article provides an overview of a SystemC-based Transaction Level Modeling (TLM) methodology for the rapid creation of SoC platform models. First a brief overview of the ESL design tasks and the corresponding modeling requirements is given. The main topic is a methodology for the efficient creation of transaction-level peripheral models. Those are usually specific for a particular SoC platform and have to be created by the ESL user.
Click here to access this paper (PDF file)
Related Semiconductor IP
- Post-Quantum Digital Signature IP Core
- Compact Embedded RISC-V Processor
- Power-OK Monitor
- RISC-V-Based, Open Source AI Accelerator for the Edge
- Securyzr™ neo Core Platform
Related White Papers
- SystemC: Key modeling concepts besides TLM to boost your simulation performance
- Using IP-XACT Metadata for a TLM Modeling Flow
- Open-Source Design of Heterogeneous SoCs for AI Acceleration: the PULP Platform Experience
- Unified Modeling in C++ & SystemC
Latest White Papers
- DRsam: Detection of Fault-Based Microarchitectural Side-Channel Attacks in RISC-V Using Statistical Preprocessing and Association Rule Mining
- ShuffleV: A Microarchitectural Defense Strategy against Electromagnetic Side-Channel Attacks in Microprocessors
- Practical Considerations of LDPC Decoder Design in Communications Systems
- A Direct Memory Access Controller (DMAC) for Irregular Data Transfers on RISC-V Linux Systems
- A logically correct SoC design isn’t an optimized design