Targeting SoC address decoder faults using functional patterns
Aashish Mittal, Glenn Carson, and Nitin Goel, Freescale Semiconductor
embedded.com (September 28, 2014)
Even though you have thoroughly verified your SoC design during the development cycle, sometimes critical faults during manufacturing can lead to failure in the field, one of the most serious of which is the address decoder stuck-at fault [1]. This is a critical fault that must be tested for on each and every piece of silicon that needs to pass qualification for an industry standard [2].
Testing of RAM and other memories come under the scope of Design for Test (DFT). It is generally achieved by implementing a number of algorithms which are either part of MBIST (memory built-in self test) delivered by a third party or DFT patterns targeted for particular faults in memory [3]. Conventionally, no special fault detection technique is used for an address decoder as they are assumed to be covered with array testing. Some of earlier MBIST controllers do not support Algos for checking ASOF faults, so our approach is to use a functional tester pattern to catch these faults on silicon.
To read the full article, click here
Related Semiconductor IP
- Post-Quantum Digital Signature IP Core
- Compact Embedded RISC-V Processor
- Power-OK Monitor
- RISC-V-Based, Open Source AI Accelerator for the Edge
- Securyzr™ neo Core Platform
Related White Papers
- An Efficient Device for Forward Collision Warning Using Low Cost Stereo Camera & Embedded SoC
- A cost-effective and highly productive Framework for IP Integration in SoC using pre-defined language sensitive Editors (LSE) templates and effectively using System Verilog Interfaces
- Safety Verification and Optimization of Automotive Ethernet Using Dedicated SoC FIT Rates
- Smart Tracking of SoC Verification Progress Using Synopsys' Hierarchical Verification Plan (HVP)
Latest White Papers
- DRsam: Detection of Fault-Based Microarchitectural Side-Channel Attacks in RISC-V Using Statistical Preprocessing and Association Rule Mining
- ShuffleV: A Microarchitectural Defense Strategy against Electromagnetic Side-Channel Attacks in Microprocessors
- Practical Considerations of LDPC Decoder Design in Communications Systems
- A Direct Memory Access Controller (DMAC) for Irregular Data Transfers on RISC-V Linux Systems
- A logically correct SoC design isn’t an optimized design