Targeting SoC address decoder faults using functional patterns
Aashish Mittal, Glenn Carson, and Nitin Goel, Freescale Semiconductor
embedded.com (September 28, 2014)
Even though you have thoroughly verified your SoC design during the development cycle, sometimes critical faults during manufacturing can lead to failure in the field, one of the most serious of which is the address decoder stuck-at fault [1]. This is a critical fault that must be tested for on each and every piece of silicon that needs to pass qualification for an industry standard [2].
Testing of RAM and other memories come under the scope of Design for Test (DFT). It is generally achieved by implementing a number of algorithms which are either part of MBIST (memory built-in self test) delivered by a third party or DFT patterns targeted for particular faults in memory [3]. Conventionally, no special fault detection technique is used for an address decoder as they are assumed to be covered with array testing. Some of earlier MBIST controllers do not support Algos for checking ASOF faults, so our approach is to use a functional tester pattern to catch these faults on silicon.
To read the full article, click here
Related Semiconductor IP
- USB 4.0 V2 PHY - 4TX/2RX, TSMC N3P , North/South Poly Orientation
- FH-OFDM Modem
- NFC wireless interface supporting ISO14443 A and B with EEPROM on SMIC 180nm
- PQC CRYSTALS core for accelerating NIST FIPS 202 FIPS 203 and FIPS 204
- USB Full Speed Transceiver
Related White Papers
- An Efficient Device for Forward Collision Warning Using Low Cost Stereo Camera & Embedded SoC
- A cost-effective and highly productive Framework for IP Integration in SoC using pre-defined language sensitive Editors (LSE) templates and effectively using System Verilog Interfaces
- Safety Verification and Optimization of Automotive Ethernet Using Dedicated SoC FIT Rates
- Smart Tracking of SoC Verification Progress Using Synopsys' Hierarchical Verification Plan (HVP)
Latest White Papers
- FastPath: A Hybrid Approach for Efficient Hardware Security Verification
- Automotive IP-Cores: Evolution and Future Perspectives
- TROJAN-GUARD: Hardware Trojans Detection Using GNN in RTL Designs
- How a Standardized Approach Can Accelerate Development of Safety and Security in Automotive Imaging Systems
- SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models