"So, when will you be done with your design?"
Jeroen Fonderie, Touchstone Semiconductor
EDN (March 4, 2013)
Not exactly the question a typical design engineer is looking forward to. You’re at the start of a new project and it is time to commit to a development schedule. Now what? Your first instinct is to be vague. Use verbs like “should” and “hope” and lots of conditional statements. But you know that’s not going to fly. You can give your best estimate. But you’re usually too optimistic and then you will get yelled at when you don’t meet that commitment.
Or you can pad the heck out of it. At least that way you know you will not be bothered for many weeks. But now your manager and your peers may start to see you as a sandbagger whose input is not to be taken seriously. So what is the best way to come up with a schedule for the design phase of your project?
To read the full article, click here
Related Semiconductor IP
- Flexible Pixel Processor Video IP
- Complex Digital Up Converter
- Bluetooth Low Energy 6.0 Digital IP
- Verification IP for Ultra Ethernet (UEC)
- MIPI SWI3S Manager Core IP
Related White Papers
- EDA in the Cloud Will be Key to Rapid Innovative SoC Design
- Add Security And Supply Chain Trust To Your ASIC Or SoC With eFPGAs
- 7 warning signs that you should be concerned about your IP provider
- Setting up secure VPN connections with cryptography offloaded to your Altera SoC FPGA
Latest White Papers
- RISC-V basics: The truth about custom extensions
- Unlocking the Power of Digital Twins in ASICs with Adaptable eFPGA Hardware
- Security Enclave Architecture for Heterogeneous Security Primitives for Supply-Chain Attacks
- relOBI: A Reliable Low-latency Interconnect for Tightly-Coupled On-chip Communication
- Enabling Space-Grade AI/ML with RISC-V: A Fully European Stack for Autonomous Missions