"So, when will you be done with your design?"
Jeroen Fonderie, Touchstone Semiconductor
EDN (March 4, 2013)
Not exactly the question a typical design engineer is looking forward to. You’re at the start of a new project and it is time to commit to a development schedule. Now what? Your first instinct is to be vague. Use verbs like “should” and “hope” and lots of conditional statements. But you know that’s not going to fly. You can give your best estimate. But you’re usually too optimistic and then you will get yelled at when you don’t meet that commitment.
Or you can pad the heck out of it. At least that way you know you will not be bothered for many weeks. But now your manager and your peers may start to see you as a sandbagger whose input is not to be taken seriously. So what is the best way to come up with a schedule for the design phase of your project?
To read the full article, click here
Related Semiconductor IP
- RVA23, Multi-cluster, Hypervisor and Android
- 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
- NPU IP Core for Mobile
- RISC-V AI Acceleration Platform - Scalable, standards-aligned soft chiplet IP
- H.264 Decoder
Related White Papers
- 7 warning signs that you should be concerned about your IP provider
- EDA in the Cloud Will be Key to Rapid Innovative SoC Design
- Safeguard your FPGA system with a secure authenticator
- Setting up secure VPN connections with cryptography offloaded to your Altera SoC FPGA
Latest White Papers
- QiMeng: Fully Automated Hardware and Software Design for Processor Chip
- RISC-V source class riscv_asm_program_gen, the brain behind assembly instruction generator
- Concealable physical unclonable functions using vertical NAND flash memory
- Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution
- Transition Fixes in 3nm Multi-Voltage SoC Design