Programmable logic carves further into the ASIC's territory
The key issues surrounding programmable logic never seem to change. If your quantity is going to be less than X, design your circuit with programmable logic. If you need more than X, go with an ASIC. Over the last few years, X has been increasing. Not too long ago, X was measured in the thousands (as in 100,000). Today, there are examples where programmable logic devices are employed into the millions.
The reasons for X (and the moving X), have to do with the per-unit cost of the programmable logic ICs versus the NREs associated with ASICs. While the NREs are on the rise, the programmable chips are coming down, fairly significantly.
According to one industry insider, in the United States, about one-third of all ASICs ship less than 50,000 devices over their lifetime. Around 47% ship 100,000 over their lifetime. If you look at NREs today, certainly for the latest process technologies, you could be looking at $500,000 for an ASIC spin. And not too many design teams get it done right on the first spin.
When you add the amortized NRE to the cost of the ASIC, the programmable part becomes pretty attractive. The programmable-logic industry is nearing the point where it can offer solutions for under $20 that basically make ASICs not viable for anything other than quantities in the millions. Add that to the fact the programmable part can get you to market faster.
Read more ....
Related Semiconductor IP
- HBM4 PHY IP
- eFuse Controller IP
- Secure Storage Solution for OTP IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- MIPI D-PHY and FPD-Link (LVDS) Combinational Transmitter for TSMC 22nm ULP
Related Articles
- Embedded Systems: Programmable Logic -> Focus is on the best ASIC design flow
- FPGAs - The Logical Solution to the Microcontroller Shortage
- Amba bus may move MIPS into ARM territory
- Embedded Systems: Programmable Logic -> Programming enters designer's core
Latest Articles
- Making Strong Error-Correcting Codes Work Effectively for HBM in AI Inference
- Sensitivity-Aware Mixed-Precision Quantization for ReRAM-based Computing-in-Memory
- ElfCore: A 28nm Neural Processor Enabling Dynamic Structured Sparse Training and Online Self-Supervised Learning with Activity-Dependent Weight Update
- A 14ns-Latency 9Gb/s 0.44mm² 62pJ/b Short-Blocklength LDPC Decoder ASIC in 22FDX
- Pipeline Stage Resolved Timing Characterization of FPGA and ASIC Implementations of a RISC V Processor