Productivity Boost in Embedded Processor Design
by Rainer Leupers, Tim Kogel, Heinrich Meyr, Andreas Hoffmann, Uri Mayer,Steffen Buch and Mario Steinert
Increased flexibility and efficiency are requirements of embedded processors (EPs) for today's complex SoC designs. This article addresses traditional methodologies that are used in EP design, and some challenges designers are facing today. It will also describe new methodologies and technologies that are emerging to dramatically shorten the embedded processor design cycle.
Increased flexibility and efficiency are requirements of embedded processors (EPs) for today's complex SoC designs. This article addresses traditional methodologies that are used in EP design, and some challenges designers are facing today. It will also describe new methodologies and technologies that are emerging to dramatically shorten the embedded processor design cycle.
Related Semiconductor IP
- HBM4 PHY IP
- eFuse Controller IP
- Secure Storage Solution for OTP IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- MIPI D-PHY and FPD-Link (LVDS) Combinational Transmitter for TSMC 22nm ULP
Related Articles
- Emerging Trends and Challenges in Embedded System Design
- The role of cache in AI processor design
- How to boost verification productivity
- Standard design constraints: The next productivity boost for custom design
Latest Articles
- Making Strong Error-Correcting Codes Work Effectively for HBM in AI Inference
- Sensitivity-Aware Mixed-Precision Quantization for ReRAM-based Computing-in-Memory
- ElfCore: A 28nm Neural Processor Enabling Dynamic Structured Sparse Training and Online Self-Supervised Learning with Activity-Dependent Weight Update
- A 14ns-Latency 9Gb/s 0.44mm² 62pJ/b Short-Blocklength LDPC Decoder ASIC in 22FDX
- Pipeline Stage Resolved Timing Characterization of FPGA and ASIC Implementations of a RISC V Processor