How to test the interconnections between FPGAs on a high-density FPGA-based board
By Rajendra C Turakani and Ritesh Ramesh Parekh, Ittiam Systems.
Apr 11 2007 (14:17 PM), Programmable Logic DesignLine
Abstract
High-density FPGA-based boards are widely being used for logic development and verification before taping out the actual IC. On a high-density FPGA-based board where multiple FPGAs are interconnected with hundreds of signals, checking and validating the interconnections between the FPGAs becomes a very challenging task. This article describes how challenging the problem is and also suggests a simple, effective, and generic solution to check the signal connectivity between the FPGAs. The method also helps the designer to identify and locate faults, if any, on the board which otherwise would have been a very cumbersome task. This article also proposes a method to efficiently generate the test code, most of which could be automated.
To read the full article, click here
Related Semiconductor IP
- USB 4.0 V2 PHY - 4TX/2RX, TSMC N3P , North/South Poly Orientation
- FH-OFDM Modem
- NFC wireless interface supporting ISO14443 A and B with EEPROM on SMIC 180nm
- PQC CRYSTALS core for accelerating NIST FIPS 202 FIPS 203 and FIPS 204
- USB Full Speed Transceiver
Related White Papers
- High Density FPGA Package BIST Technique
- What! How big did you say that FPGA is? (Team-design for FPGAs)
- Prototyping Mesh-of-Tree NOC Based MPSOC on Mesh-of-Tree FPGA Devices
- How to Reduce FPGA Logic Cell Usage by >x5 for Floating-Point FFTs
Latest White Papers
- FastPath: A Hybrid Approach for Efficient Hardware Security Verification
- Automotive IP-Cores: Evolution and Future Perspectives
- TROJAN-GUARD: Hardware Trojans Detection Using GNN in RTL Designs
- How a Standardized Approach Can Accelerate Development of Safety and Security in Automotive Imaging Systems
- SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models