How to test the interconnections between FPGAs on a high-density FPGA-based board
By Rajendra C Turakani and Ritesh Ramesh Parekh, Ittiam Systems.
Apr 11 2007 (14:17 PM), Programmable Logic DesignLine
Abstract
High-density FPGA-based boards are widely being used for logic development and verification before taping out the actual IC. On a high-density FPGA-based board where multiple FPGAs are interconnected with hundreds of signals, checking and validating the interconnections between the FPGAs becomes a very challenging task. This article describes how challenging the problem is and also suggests a simple, effective, and generic solution to check the signal connectivity between the FPGAs. The method also helps the designer to identify and locate faults, if any, on the board which otherwise would have been a very cumbersome task. This article also proposes a method to efficiently generate the test code, most of which could be automated.
To read the full article, click here
Related Semiconductor IP
- RVA23, Multi-cluster, Hypervisor and Android
- 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
- NPU IP Core for Mobile
- H.264 Decoder
- V-by-One® HS plus Tx/Rx IP
Related White Papers
- High Density FPGA Package BIST Technique
- What! How big did you say that FPGA is? (Team-design for FPGAs)
- Prototyping Mesh-of-Tree NOC Based MPSOC on Mesh-of-Tree FPGA Devices
- How to Reduce FPGA Logic Cell Usage by >x5 for Floating-Point FFTs
Latest White Papers
- RISC-V source class riscv_asm_program_gen, the brain behind assembly instruction generator
- Concealable physical unclonable functions using vertical NAND flash memory
- Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution
- Transition Fixes in 3nm Multi-Voltage SoC Design
- CXL Topology-Aware and Expander-Driven Prefetching: Unlocking SSD Performance