How to prevent FPGA-based projects from going astray
Adam Taylor, E2V
embedded.com (February 22, 2017)
During the course of my career, I have been involved with developing a number of FPGA designs for some really interesting projects. Sadly, I have also been involved in rescuing several FPGA designs that have gone badly astray. As I worked on these problem designs, it became apparent that -- although the target applications and the members of the development teams were different -- the designs shared some common points that doomed them to failure before the first engineer even sat down to write the first line of HDL code.
With this in mind, I thought I would run through five common issues that I've observed as part of rescuing these projects. These issues are as follows:
To read the full article, click here
Related Semiconductor IP
- eUSB2V2.0 Controller + PHY IP
- I/O Library with LVDS in SkyWater 90nm
- 50G PON LDPC Encoder/Decoder
- UALink Controller
- RISC-V Debug & Trace IP
Related Articles
- Going from 8- to 32-bit MCUs takes tools
- Going from GDSII to OASIS
- How to improve FPGA-based ASIC prototyping with SystemVerilog
- How to transform video SerDes from a nightmare to a dream
Latest Articles
- QMC: Efficient SLM Edge Inference via Outlier-Aware Quantization and Emergent Memories Co-Design
- ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Design
- COVERT: Trojan Detection in COTS Hardware via Statistical Activation of Microarchitectural Events
- A Reconfigurable Framework for AI-FPGA Agent Integration and Acceleration
- Veri-Sure: A Contract-Aware Multi-Agent Framework with Temporal Tracing and Formal Verification for Correct RTL Code Generation