How to prevent FPGA-based projects from going astray
Adam Taylor, E2V
embedded.com (February 22, 2017)
During the course of my career, I have been involved with developing a number of FPGA designs for some really interesting projects. Sadly, I have also been involved in rescuing several FPGA designs that have gone badly astray. As I worked on these problem designs, it became apparent that -- although the target applications and the members of the development teams were different -- the designs shared some common points that doomed them to failure before the first engineer even sat down to write the first line of HDL code.
With this in mind, I thought I would run through five common issues that I've observed as part of rescuing these projects. These issues are as follows:
To read the full article, click here
Related Semiconductor IP
- Process/Voltage/Temperature Sensor with Self-calibration (Supply voltage 1.2V) - TSMC 3nm N3P
- USB 20Gbps Device Controller
- SM4 Cipher Engine
- Ultra-High-Speed Time-Interleaved 7-bit 64GSPS ADC on 3nm
- Fault Tolerant DDR2/DDR3/DDR4 Memory controller
Related White Papers
- Going from 8- to 32-bit MCUs takes tools
- Going from GDSII to OASIS
- How to improve FPGA-based ASIC prototyping with SystemVerilog
- How to transform video SerDes from a nightmare to a dream
Latest White Papers
- Fault Injection in On-Chip Interconnects: A Comparative Study of Wishbone, AXI-Lite, and AXI
- eFPGA – Hidden Engine of Tomorrow’s High-Frequency Trading Systems
- aTENNuate: Optimized Real-time Speech Enhancement with Deep SSMs on RawAudio
- Combating the Memory Walls: Optimization Pathways for Long-Context Agentic LLM Inference
- Hardware Acceleration of Kolmogorov-Arnold Network (KAN) in Large-Scale Systems