High-definition video scaler ASIC development from FPGA
videsignline.com, September 29, 2006
How a high-definition video scaler ASIC was quickly created using a flexible FPGA-to-ASIC conversion flow. This ensured reproduction of the FPGA functionality and enabled first time fully functional silicon supporting video resolutions up to 1080p.
Consumers are buying ever larger numbers of liquid crystal displays (LCD), plasma and digital light processing (DLP) based systems. As digital displays continue to offer higher resolution capabilities, high quality video scaling is becoming a key feature for the new generation of high definition video sources.
This article details the implementation and verification flows of a high-definition video scaler ASIC implemented in a 0.18um standard cell technology. The Anchor Bay Technology application targets the consumer market space for high-definition video sources (for example, HD-DVD and Blu-ray players). Achieving quick time-to-market was critical for the success of the project, in addition to beating competitive products in cost, features and ease-of-use. An FPGA prototype was used for at-speed verification of all functionality, especially image quality enhancements.
To read the full article, click here
Related Semiconductor IP
- Sine Wave Frequency Generator
- CAN XL Verification IP
- Rad-Hard GPIO, ODIO & LVDS in SkyWater 90nm
- 1.22V/1uA Reference voltage and current source
- 1.2V SLVS Transceiver in UMC 110nm
Related White Papers
- Generating High Speed CSI2 Video by an FPGA
- Micros benefit from ASIC heritage
- Meeting the Challenge of Real-Time Video Encoding: Migrating From H.263 to H.264
- Processor Architecture for High Performance Video Decode
Latest White Papers
- OmniSim: Simulating Hardware with C Speed and RTL Accuracy for High-Level Synthesis Designs
- Balancing Power and Performance With Task Dependencies in Multi-Core Systems
- LLM Inference with Codebook-based Q4X Quantization using the Llama.cpp Framework on RISC-V Vector CPUs
- PCIe 5.0: The universal high-speed interconnect for High Bandwidth and Low Latency Applications Design Challenges & Solutions
- Basilisk: A 34 mm2 End-to-End Open-Source 64-bit Linux-Capable RISC-V SoC in 130nm BiCMOS