Foundation IP for 7nm FinFETs: Design and Implementation
Jamil Kawa, Synopsys Fellow, Synopsys
Learn about the challenges of IP design and implementation for 7nm FinFETs. Along with the performance and area benefits that the node brings, designers must understand the significant technical challenges stemming from increasing variability associated with tighter pitches and more complex lithography steps. Design for variability and reliability considerations will require comprehensive modeling and analysis as well as advanced circuit techniques such as on chip sensing and compensation.
Related Semiconductor IP
- RVA23, Multi-cluster, Hypervisor and Android
- 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
- NPU IP Core for Mobile
- RISC-V AI Acceleration Platform - Scalable, standards-aligned soft chiplet IP
- H.264 Decoder
Related White Papers
- Design and Implementation of Test Infrastructure for Higher Parallel Wafer Level Testing of System-on-Chip
- Design and implementation of a hardened cryptographic coprocessor for a RISC-V 128-bit core
- Agile Analog's Approach to Analog IP Design and Quality --- Why "Silicon Proven" is NOT What You Think
- Integrating VESA DSC and MIPI DSI in a System-on-Chip (SoC): Addressing Design Challenges and Leveraging Arasan IP Portfolio
Latest White Papers
- QiMeng: Fully Automated Hardware and Software Design for Processor Chip
- RISC-V source class riscv_asm_program_gen, the brain behind assembly instruction generator
- Concealable physical unclonable functions using vertical NAND flash memory
- Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution
- Transition Fixes in 3nm Multi-Voltage SoC Design