Creating multi-standard, multi-resolution video engines using configurable processors
September 15, 2006 -- videsignline.com
Customize the processor to your video application by creating instructions, register files, functional units and interfaces that accelerate the processing.
The explosive growth of consumer electronics and, specifically, handheld devices such as cellular phones, PDAs, and portable media players (PMPs) has drastically changed the requirements placed on the end-silicon providers. These silicon providers can no longer design ICs that are targeted at only one or two multimedia codecs or wireless standards. Consumers expect their devices to play media from different sources, coded using different standards, and downloaded using a variety of different wireless standards. Therefore, a new, more flexible design approach must be taken that provides for easy adoption of new media standards. In this article, we focus on the challenges and opportunities for video decoder and encoder engines.
To read the full article, click here
Related Semiconductor IP
- Sine Wave Frequency Generator
- CAN XL Verification IP
- Rad-Hard GPIO, ODIO & LVDS in SkyWater 90nm
- 1.22V/1uA Reference voltage and current source
- 1.2V SLVS Transceiver in UMC 110nm
Related White Papers
- A configurable FPGA-based multi-channel high-definition Video Processing Platform
- Performance Evaluation of Inter-Processor Communication Mechanisms on the Multi-Core Processors using a Reconfigurable Device
- Configurable Processors for Video Processing SOCs
- Power Optimization using Multi BIT flops and MIMCAPs in 16nm technology and below
Latest White Papers
- On the Thermal Vulnerability of 3D-Stacked High-Bandwidth Memory Architectures
- OmniSim: Simulating Hardware with C Speed and RTL Accuracy for High-Level Synthesis Designs
- Balancing Power and Performance With Task Dependencies in Multi-Core Systems
- LLM Inference with Codebook-based Q4X Quantization using the Llama.cpp Framework on RISC-V Vector CPUs
- PCIe 5.0: The universal high-speed interconnect for High Bandwidth and Low Latency Applications Design Challenges & Solutions