Configurable Processors: Ready for Prime Time
By David Fritz, ARC International
The configurable processor has been around for some years, with the promise of improved performance and reduced power consumption and real estate area. But is only recently that its promise has begun to be matched with design and verification tools. David Fritz looks at today’s options.
Click here to read more....
Related Semiconductor IP
- LPDDR6/5X/5 PHY V2 - Intel 18A-P
- ML-KEM Key Encapsulation & ML-DSA Digital Signature Engine
- MIPI SoundWire I3S Peripheral IP
- ML-DSA Digital Signature Engine
- P1619 / 802.1ae (MACSec) GCM/XTS/CBC-AES Core
Related Articles
- Reconfigurable processors make move into big time
- Reduce SOC simulation and development time by designing with processors, not gates
- Tuning Fork - A Tool For Optimizing Parallel Configurable Processors
- Configurable processors or RTL -- evaluating the tradeoffs
Latest Articles
- FPGA-Accelerated RISC-V ISA Extensions for Efficient Neural Network Inference on Edge Devices
- MultiVic: A Time-Predictable RISC-V Multi-Core Processor Optimized for Neural Network Inference
- AnaFlow: Agentic LLM-based Workflow for Reasoning-Driven Explainable and Sample-Efficient Analog Circuit Sizing
- FeNN-DMA: A RISC-V SoC for SNN acceleration
- Multimodal Chip Physical Design Engineer Assistant