Characterizing licensable core performance; Find out why comparing processor cores is tricky and learn what to look for.

[Editor's note: If you are unfamiliar with the concepts of chip fabrication, the article "Push performance and power beyond the data sheet" provides some useful background.]
Comparing licensable processor cores and quantifying their relative performance is challenging. Unlike processor chips, there are many different ways in which licensable cores can be configured, implemented, and fabricated, each of which yields a different combination of speed, area, and power consumption. Particularly for digital signal processing applications (which tend to push the limits on one or more of these metrics) it's essential to have reliable and accurate performance data.
To make apples-to-apples comparisons between cores you'll need to pin down a consistent set of assumptions. In this article, we'll discuss some of the factors to consider when assessing and comparing licensable cores for digital signal processing.
To read the full article, click here
Related Semiconductor IP
- Multi-channel Ultra Ethernet TSS Transform Engine
- Configurable CPU tailored precisely to your needs
- Ultra high-performance low-power ADC
- HiFi iQ DSP
- CXL 4 Verification IP
Related Articles
- Agile Analog's Approach to Analog IP Design and Quality --- Why "Silicon Proven" is NOT What You Think
- Top 5 Reasons why CPU is the Best Processor for AI Inference
- Interstellar: Fully Partitioned and Efficient Security Monitoring Hardware Near a Processor Core for Protecting Systems against Attacks on Privileged Software
- Find out what's really inside the iPod; Reuse of components is a good design practice for similar applications, including mobile handsets
Latest Articles
- GenAI for Systems: Recurring Challenges and Design Principles from Software to Silicon
- Creating a Frequency Plan for a System using a PLL
- RISCover: Automatic Discovery of User-exploitable Architectural Security Vulnerabilities in Closed-Source RISC-V CPUs
- MING: An Automated CNN-to-Edge MLIR HLS framework
- Fault Tolerant Design of IGZO-based Binary Search ADCs