Characterizing licensable core performance; Find out why comparing processor cores is tricky and learn what to look for.
[Editor's note: If you are unfamiliar with the concepts of chip fabrication, the article "Push performance and power beyond the data sheet" provides some useful background.]
Comparing licensable processor cores and quantifying their relative performance is challenging. Unlike processor chips, there are many different ways in which licensable cores can be configured, implemented, and fabricated, each of which yields a different combination of speed, area, and power consumption. Particularly for digital signal processing applications (which tend to push the limits on one or more of these metrics) it's essential to have reliable and accurate performance data.
To make apples-to-apples comparisons between cores you'll need to pin down a consistent set of assumptions. In this article, we'll discuss some of the factors to consider when assessing and comparing licensable cores for digital signal processing.
To read the full article, click here
Related Semiconductor IP
- Post-Quantum Digital Signature IP Core
- Compact Embedded RISC-V Processor
- Power-OK Monitor
- RISC-V-Based, Open Source AI Accelerator for the Edge
- Securyzr™ neo Core Platform
Related White Papers
- Agile Analog's Approach to Analog IP Design and Quality --- Why "Silicon Proven" is NOT What You Think
- Why Interlaken is a great choice for architecting chip to chip communications in AI chips
- Top 5 Reasons why CPU is the Best Processor for AI Inference
- Interstellar: Fully Partitioned and Efficient Security Monitoring Hardware Near a Processor Core for Protecting Systems against Attacks on Privileged Software
Latest White Papers
- DRsam: Detection of Fault-Based Microarchitectural Side-Channel Attacks in RISC-V Using Statistical Preprocessing and Association Rule Mining
- ShuffleV: A Microarchitectural Defense Strategy against Electromagnetic Side-Channel Attacks in Microprocessors
- Practical Considerations of LDPC Decoder Design in Communications Systems
- A Direct Memory Access Controller (DMAC) for Irregular Data Transfers on RISC-V Linux Systems
- A logically correct SoC design isn’t an optimized design