Opinion: Challenges and techniques to meet power budget in complex systems
Christian Caillon, C Cube Hightech
EETimes (4/5/2012 1:19 PM EDT)
Reducing the power consumption of electronic equipments is becoming a key differentiator for performances and costs. It is obvious for portable equipments such as smartphones or tablets but also for devices such as set top boxes or TV where thermal problems can occur if power consumption is not well managed. It is really a big challenge for system architects and IC designers to meet the power budget provided by the OEM’s specifications and to make early decisions to manage power. The power reduction methods such as clock gating, power gating, memory gating, DVFS, multi-Vt, transistor dynamic body biasing are now well known but the problem is how to optimize the use of this set of techniques to surely reach the power budget and device specifications. On top of that, engineering time and global effort provided by engineers to meet power specifications is growing with system complexity impacting the time to market. It can be considered that 25% of time is spent by engineers to work on power reduction techniques and analysis. Due to the convergence of multiple applications in smartphones and tablets (telecommunications, internet, games, and multiple connectivity protocols) we can also observe that each new generation of equipment is introducing more complex use cases multiplying the number of power management scenarios.
To read the full article, click here
Related Semiconductor IP
- USB 4.0 V2 PHY - 4TX/2RX, TSMC N3P , North/South Poly Orientation
- FH-OFDM Modem
- NFC wireless interface supporting ISO14443 A and B with EEPROM on SMIC 180nm
- PQC CRYSTALS core for accelerating NIST FIPS 202 FIPS 203 and FIPS 204
- USB Full Speed Transceiver
Related White Papers
- Time Interleaving of Analog to Digital Converters: Calibration Techniques, Limitations & what to look in Time Interleaved ADC IP prior to licensing
- Integrating VESA DSC and MIPI DSI in a System-on-Chip (SoC): Addressing Design Challenges and Leveraging Arasan IP Portfolio
- 8051s in Modern Systems: Interfacing to AMBA Buses
- From I2C to I3C: Evolution of Two-Wire Communication in Embedded Systems
Latest White Papers
- FastPath: A Hybrid Approach for Efficient Hardware Security Verification
- Automotive IP-Cores: Evolution and Future Perspectives
- TROJAN-GUARD: Hardware Trojans Detection Using GNN in RTL Designs
- How a Standardized Approach Can Accelerate Development of Safety and Security in Automotive Imaging Systems
- SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models