Virtual prototyping speeds mixed-signal IC design
(08/21/2006 9:00 AM EDT), EE Times
Current design trends for high performance systems-on-chip (SoCs) are prompting designers to adopt more and more analog/mixed signal (AMS) contents in the overall design. Unlike digital designs that are quantized in the time and amplitude domains, AMS designs are more complex because performance, noise and other factors need to be controlled continuously in time and amplitude domain with very strict tolerances.
While the cost and performance benefits of SoCs are well known, in reality the complexity of design and verification of AMS ICs are making cutting-edge designs very time consuming and error prone, hence cost ineffective. The problem is further exacerbated by the lack of skilled AMS designers and adequate EDA tools.
To read the full article, click here
Related Semiconductor IP
- Wi-Fi 7(be) RF Transceiver IP in TSMC 22nm
- PUF FPGA-Xilinx Premium with key wrap
- ASIL-B Ready PUF Hardware Premium with key wrap and certification support
- ASIL-B Ready PUF Hardware Base
- PUF Software Premium with key wrap and certification support
Related White Papers
- Analog & Mixed Signal IC Debug: A high precision ADC application
- Mixed-level modeling allows IC virtual prototypes
- Efficient Verification and Virtual Prototyping of Analog and Mixed-Signal IP and SOCs Using Behavioral Models
- RTL Prototyping Brings Hardware Speeds to Functional Verification
Latest White Papers
- Boosting RISC-V SoC performance for AI and ML applications
- e-GPU: An Open-Source and Configurable RISC-V Graphic Processing Unit for TinyAI Applications
- How to design secure SoCs, Part II: Key Management
- Seven Key Advantages of Implementing eFPGA with Soft IP vs. Hard IP
- Hardware vs. Software Implementation of Warp-Level Features in Vortex RISC-V GPU