Using FPGAs to build a compact, low cost, and low power Ethernet-to-Network Processor bridge
By Ted Marena, Lattice Semiconductor
Jul 11 2007 (12:49 PM), Embedded.com
As carriers and cable providers begin rolling out triple-play and VoD services to their customers, OEMs are increasing their development efforts to roll out IP- (Internet Protocol) based systems, including PONs, CMTS, IP DSLAMs and other access and last-mile equipment. The common underlying physical layer for this is the ubiquitous Ethernet technology, now coupled with sophisticated QoS (Quality of Service) overlays.
Within this context, design engineers are devoting more design effort to connect their switched Ethernet backplanes to the system line cards and, specifically, to their Network Processors. System architects often select Ethernet Switches and Network Processors based on their individual features and rarely consider the challenge of interconnecting the two.
Design engineers are then left with the challenge of developing the bridge, fitting the solution and implementing it cost effectively. Moreover, because both interfaces run at very high speeds, power is also a significant concern. All of these challenges are addressed in this article.
Related Semiconductor IP
- nQrux® Root of Trust IP
- AXI to UCIe Bridge IP
- UCIe 2.x Controller IP
- SWI3S (SoundWire I3S Interface) Peripheral Controller Core IP
- OpenTitan-based RISC-V Secure Element
Related Articles
- How silicon and circuit optimizations help FPGAs offer lower size, power and cost in video bridging applications
- How Low Can You Go? Pushing the Limits of Transistors - Deep Low Voltage Enablement of Embedded Memories and Logic Libraries to Achieve Extreme Low Power
- Build low power video SoCs with programmable multi-core video processor IP
- A versatile Control Network of power domains in a low power SoC
Latest Articles
- Automated Pre-Silicon Verification of High-Speed DDR5 and LPDDR5/6 Memory Controllers: Closed-Loop Timing, Mode Register, and PHY Synchronization in UVM
- U-Sonic: An Open-Source 8-Channel Ultrasound Transmit IP in a 130 nm RISC-V SoC
- S-ALSA: Co-Design of Adiabatic Logic-based Sensing and Balanced Bit-Cells for Secure and Energy-Efficient MRAM
- MEGATRON: a 28nm Analog PCM CiM/Digital System-on-Chip for Edge GenAI at 57.5 TOPS/W and 1.52 Mparam/mm²
- Peregrino: A Full-Hardware Accelerator for the Complete Falcon Post-Quantum Digital Signature Scheme on Resource-Constrained Edge Devices