Using FPGAs to build a compact, low cost, and low power Ethernet-to-Network Processor bridge
By Ted Marena, Lattice Semiconductor
Jul 11 2007 (12:49 PM), Embedded.com
As carriers and cable providers begin rolling out triple-play and VoD services to their customers, OEMs are increasing their development efforts to roll out IP- (Internet Protocol) based systems, including PONs, CMTS, IP DSLAMs and other access and last-mile equipment. The common underlying physical layer for this is the ubiquitous Ethernet technology, now coupled with sophisticated QoS (Quality of Service) overlays.
Within this context, design engineers are devoting more design effort to connect their switched Ethernet backplanes to the system line cards and, specifically, to their Network Processors. System architects often select Ethernet Switches and Network Processors based on their individual features and rarely consider the challenge of interconnecting the two.
Design engineers are then left with the challenge of developing the bridge, fitting the solution and implementing it cost effectively. Moreover, because both interfaces run at very high speeds, power is also a significant concern. All of these challenges are addressed in this article.
Related Semiconductor IP
- Root of Trust (RoT)
- Fixed Point Doppler Channel IP core
- Multi-protocol wireless plaform integrating Bluetooth Dual Mode, IEEE 802.15.4 (for Thread, Zigbee and Matter)
- Polyphase Video Scaler
- Compact, low-power, 8bit ADC on GF 22nm FDX
Related White Papers
- How Low Can You Go? Pushing the Limits of Transistors - Deep Low Voltage Enablement of Embedded Memories and Logic Libraries to Achieve Extreme Low Power
- How silicon and circuit optimizations help FPGAs offer lower size, power and cost in video bridging applications
- BCD Technology: A Unified Approach to Analog, Digital, and Power Design
- Growing demand for high-speed data in consumer devices gives rise to new generation of low-end FPGAs
Latest White Papers
- Monolithic 3D FPGAs Utilizing Back-End-of-Line Configuration Memories
- Reimagining AI Infrastructure: The Power of Converged Back-end Networks
- 40G UCIe IP Advantages for AI Applications
- Recent progress in spin-orbit torque magnetic random-access memory
- What is JESD204C? A quick glance at the standard