Static timing analysis: bridging the gap between simulation and silicon
Naman Gupta and Rohit Goyal, Freescale Semiconductor, Noida, India
embedded.com (December 4, 2013)
Static Timing Analysis (STA) not only acts as a connecting link between backend and frontend design activities, but more importantly helps in bridging the gap between simulation and silicon. STA is often misconstrued to be a magical solution to the meet timing requirements. While it is undoubtedly the responsibility of STA engineers to close the timing, it is equally important for the register transfer level (RTL) designers to avoid some conspicuous errors, which we refer to as architectural pitfalls for timing.
In this article we discuss AND-gate clock gating and OR-gate clock gating use cases, some obvious and some not-so-obvious, which can serve as a guide to designers to ensure that such situations are avoided upfront in the RTL stage and thus preclude the reiteration of timing closure activities from, let’s say, clock tree synthesis (CTS) and back to logical synthesis.
We conclude the paper with a case study of an odd-frequency divider circuit that has one implementation that yields correct results in RTL simulation and the necessary changes in the algorithm to ensure that it works well on silicon.
To read the full article, click here
Related Semiconductor IP
- NFC wireless interface supporting ISO14443 A and B with EEPROM on SMIC 180nm
- DDR5 MRDIMM PHY and Controller
- RVA23, Multi-cluster, Hypervisor and Android
- CXL 3.0 Controller
- ECC7 Elliptic Curve Processor for Prime NIST Curves
Related White Papers
- Practical Applications of Statistical Static Timing Analysis
- Cell model creation for statistical timing analysis
- Reducing Turnaround Time with Hierarchical Timing Analysis
- Removing pessimism and optimism in timing analysis
Latest White Papers
- TROJAN-GUARD: Hardware Trojans Detection Using GNN in RTL Designs
- How a Standardized Approach Can Accelerate Development of Safety and Security in Automotive Imaging Systems
- SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models
- Enabling Chiplet Design Through Automation and Integration Solutions
- Shift-Left Verification: Why Early Reliability Checks Matter