Special Report: Intellectual Property

Special Report: Intellectual Property
By By John H. Mayer, EBN
June 19, 2000 (4:47 p.m. EST)
URL: http://www.eetimes.com/story/OEG20000619S0048

ndustry attention is focusing on intellectual-property cores as the need for designers to develop high-gate-count devices quickly and efficiently intensifies. By most estimates, however, the IP market is still in its infancy.

The third-party IP industry last year grew 36%, to approximately $417 million, and only a handful of suppliers-primarily those selling so-called “star” IP-are making money, according to Jordan Selburn, an analyst at Dataquest Inc., San Jose.

Still, there is widespread recognition that despite evolving business models and customer/supplier relationships, IP cores and design reuse will have a dramatic impact on the semiconductor industry in the next decade. To progress to the

next stage, however, the industry will have to address an enduring problem-IP quality.

“About 50% of the IP we purchase has some problems, either with the function itself or in some performance degradation when porting to our process technology,” said Kazu Yamada, general manager of NEC Electronics Inc.'s Technology Foundation Group in Santa Clara, Calif. “That's not a very good ratio.”

Although several industry organizations, including the Virtual Socket Interface Alliance (VSIA), have spearheaded efforts to address issues of IP quality and reusability, progress has been slow and industry consensus has been difficult to achieve.

So how can an OEM determine whether a particular IP block can be successfully integrated into a larger design and meet performance expectations?

The first question to ask, say IP suppliers, is whether the IP has been proven in silicon. “There's nothing special about IP; it's just the TTL business all over again,” said Mick O'Brien, general manager of the Inventra Division at Mentor Graphics Corp., Wilsonville, Ore. “It's very simple. The higher the volume , the better the quality. So what you need to look for is high volume.”

O'Brien sees a fairly consistent evolution in the development of most IP blocks. In most cases, the first time a piece of IP is designed, it won't work.

“As you use it with a partner or customer, you perfect it and make it work, then you sell it again and it works almost correctly the second time,” he said. “By the third or fourth time, it's starting to work off-the-shelf.”

As an IP core reaches its 10th or 15th sale, it has answered most questions, and any that do remain are typically application-oriented.

“You've run the test bench many times; you have a high degree of confidence in that test bench; you've got a high degree of confidence in the RTL; the customers have used it and know that particular core,” O'Brien said. “Everyone can buy it quickly, integrate it quickly, and they just move on to the next, more difficult part of the design.”

Some third-party IP suppliers go to the trouble of creating board design s to prove to customers the validity of their own cores. For example, it's been a common practice at Altera Inc.'s Ottawa Technology Design Center, formerly DesignPro Inc.

Altera recently acquired the Nepean, Ottawa, company to spin off board designs to prove its products. Specializing in the optical-communications segment, the center has developed IP for high-speed-access products, synchronous optical networking (Sonet/SDH), ATM, and wireless technologies, as well as a variety of design services. Customers include Ascend Communications, Applied Micro Circuits, Arris Interactive, Motorola, Newbridge Networks, and Nortel Networks.

The Altera unit includes a design group whose sole purpose is to mount a CPLD on a simple board with a few popular devices to demonstrate that the company's IP can interface to certain industry-leading parts. For example, when the company brought to market Sonet IP blocks recently, it also developed boards to demonstrate the technology's ability to interface with PMC-Sier ra's SUNY chips.

“We're not so focused on going out and buying the latest ATM or Sonet test suite,” said Eric Dormer, the founder and president of DesignPRO and now director of Altera's Ottawa Technology Design Center. “We know what the top two or three standard ASSPs are out there, and we've become pretty good at writing software drivers, so we said let's just make sure our stuff can talk to theirs.

“So we actually have a design team whose sole job is to do board designs, the GUIs, the firmware ports, and everything else necessary to make sure that we can do little reference designs and evaluation boards to show our IP works with the industry-leading chips. We validate our IP that way,” he said.

Key issues

Still, it isn't always possible to use a core that has been repeatedly proven in silicon. But how else can designers get some degree of confidence that it has been designed correctly?

A few key factors can provide some insight in predicting how an IP block will function in an SoC design, industry experts say. At the top of the list is test methodology.

Take a close look at the test methodology the IP developer used and ask whether it is compatible or can be made compatible with the test methodology you plan to employ in your ASIC. In today's deep-submicron-SoC market, it is imperative that the IP supplier insert scan chains into the block to make testing the IP, as well as the overall ASIC, as simple as possible, according to ASIC vendors.

Most leading ASIC manufacturers today require a test-bus architecture or testability circuit that offers designers access to the IP. LSI Logic Corp., for example, includes full scan capability in its Coreware IP.

Similarly, all IP developed internally at NEC must include a test-bus architecture. “It adds a little overhead, but it allows us to disclose the IP's boundary to the outside of an ASIC no matter where it's located,” Yamada said.

In the next few years, built-in-self-test (BIST) capability is expe cted to be a common feature across the industry.

LSI Logic, Milpitas, Calif., already offers RTL RAM BIST as a standard feature on all RAM in its ASICs, and is adopting tools from Logic Vision to insert logic BIST in future IP, according to company executives. Integrating BIST on-chip will enable designers to generate on-board test vectors and capture and analyze them on a block-by-block basis. It will also offer the ability to run at higher frequencies than conventional test vectors do today.

Standards compliance is another critical issue, particularly in the interface arena for functions like PCI, USB, or FireWire. A design team's decision to build or buy a PCI block off-the-shelf is most often driven by time-to-market issues.

Purchasing a PCI block will theoretically save a team significant development time, but that savings is predicated on the IP performing up to expectations. One way is to ensure that the IP meets accepted standards for PCI compliance.

Methodology is also crucial. C an the IP be integrated simply and easily into your tool flow? Are all the views available for the tools you want to use? If you are developing a customer tooling-type flow, then you may have to generate many of the needed library views, which can slow development considerably.

Design guidelines

Some ASIC manufacturers are attempting to cope with quality issues by creating strict guidelines for internal development. As part of a multiyear effort to establish a design-for-reuse culture, design groups within Motorola Inc. are encouraged to follow the company's Semiconductor Reuse Standards, which define requirements for architecture, implementation, verification, and reuse.

Along with its efforts to standardize design flows and tools across groups, Motorola has established a companywide repository in which IP blocks are rated “gold, silver, and unacceptable.” The company rewards engineers with money or recognition for developing quality reusable cores.

However, sett ing specific IP-design guidelines and ensuring they are followed are two different things, semiconductor manufacturers say.

At NEC, for example, designers developing IP in-house or buying from the outside are supposed to follow an IP-core manual that defines everything from what kind of libraries are acceptable to what level of test coverage an IP block should meet.

“We try to be very restrictive and hit very severe goals,” Yamada said. But he admits that crushing time-to-market pressures make it difficult to adhere to such strict guidelines.

“Since many of the IP [cores] we use, both developed inside as well as purchased from third parties, may not satisfy all the strict criteria we have, we're starting to transition to a little more relaxed stance,” he said. “For example, test suites have to be strictly defined, but as long as it's there and the synthesis script is there, then we might start to use a piece of IP even if it's not proven in silicon just to meet time-to-market goals.”

Anothe r option is to turn to a third-party evaluation program. OpenMORE, a joint program developed by Mentor Graphics and Synopsys Inc., San Jose, evaluates the reusability of hard and soft IP for SoC designs and assigns a relative score for each block.

Based on the second edition of the Reuse Methodology Manual (RMM) written by the two companies, OpenMORE provides a set of rules and guidelines drawn from the Synopsys OpenMORE (Open Measure of Reuse Excellence) program as well as key specifications from the VSIA. It also integrates input from a variety of industry groups, including Virtual Chip Exchange, Design & Reuse, and Reusable Application-Specific Intellectual Property Developers.

The program attempts to determine how closely an IP designer followed approximately 180 rules for designing soft IP and 90 rules for hard IP described in the RMM and VISA specifications. The rules range from how the designer handled clocking to documentation.

“It's a detailed list of how you performed the design for this particular IP,” O'Brien said. “By looking at the results of an OpenMORE rating, customers are able to get some degree of confidence as to whether this piece of IP is going to be something that they can use, something they can reuse, and something they can confidently believe will work for them.”

Institutionalizing reuse

Ultimately, the best strategy is for individual companies to institutionalize a comprehensive IP- reuse design methodology. But IP and ASIC suppliers agree that while it is relatively easy to hard-code a function for one-time use, it is much more difficult to craft a piece of IP that will be completely reusable when another designer from another group comes back to reuse it months or years later.

“You have to think about it completely differently from the start,” O'Brien said. “You can design a piece of IP to be used once and once only and it will take you 100% of the effort. If you took another group of engineers and said, we want you to design th is so it's completely reusable across not only our company, but across other companies throughout the world, the amount of time and effort they would have to invest would be anywhere from 200% to 400%.”

The challenge companies continually face is deciding whether it's better to get the immediate product to market as quickly as possible or to invest in a reuse methodology that may initially take longer to design.

“The initial idea behind our IP-core manual was that everyone would follow the manual so that they could start from scratch with reusability in mind,” NEC's Yamada said. “But the fact is, that rarely happens because each designer is pushed by time-to-market and is trying to optimize performance and size of his or her own chip.”

Much depends on the organization's goal, O'Brien said. “Do I want to get to market instantaneously with the first product, or am I, let's say, a massive telecommunications manufacturer that is building 100 designs using this function every year; and is it better fo r me to put together the institutionalized design methodology so the first three designs take a long time, but the last 97 designs come to market much quicker?”

A number of companies, particularly Mentor, have developed healthy consulting businesses advising others on how to build the necessary infrastructure to institutionalize a reuse methodology across their organization. Although the rationale for a reuse methodology is slowly gaining acceptance, it is still unclear how companies will implement it.

“We've been struggling with how to correct an attitude where everyone thinks about their most immediate project,” Yamada said. “But we've come to the conclusion that you can't force people to do something on top of what they need to do and spend more time to let someone else later on use the core because they're under pressure.”

To encourage reuse, NEC has developed an intranet that enables designers to place all the IP they have developed (including those under construction) and exchange data. Bu t despite this infrastructure, NEC is far from following a development strategy in which each IP block developed in-house is 100% reusable.

“We're not at that stage yet, and it may never happen that way,” Yamada said. ”Instead, we've decided to let each designer just do their job and put their IP onto the table and let the other guys think about how to reuse them.”

John H. Mayer is a freelance writer based in Belmont, Mass.