Simulating and debugging multicore behavior

Multicore microprocessor chips are on their way, and they're going to further complicate the task facing embedded software developers. Of course, multiprocessor systems aren't new. Chips with multiple heterogeneous (different) processors, such as a RISC and a DSP, have been around for years. In fact, nearly every modern cell phone contains just such a pair.

What's new is that the number of microprocessors is dramatically increasing in order to handle the equally dramatic increase in system-on-a-chip (SoC) software content, and that these processors generally share cache memory. This approach, known as shared-memory multiprocessing or symmetric multiprocessing (SMP), adds a whole new level of complexity because software will normally need to be dynamically partitioned across the processors. Traditional static partitioning won't work.

Moreover, design teams are frequently using parallel processing, or true concurrency, to meet the system's performance specification within its power constraints. The combination of SMP and true concurrency further exacerbates the software development, validation, and debug problems to the point where traditional software-development approaches are breaking.

In this article I'll discuss these trends, explore their development problems, and describe a behavior-accurate simulation that you can use to solve them.

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