Enhance circuit timing design with programmable clock generators (Part 1 of 2)

By Lin Wu, Product Marketing Manager, Texas Instruments
Planet Analog -- (06/03/08, 05:36:04 PM EDT)

As clocks speed increase and the number of clocks increases, a programmable clock generator may offer a better system and EMI design solution

Abstact

As digital systems migrate towards increased integration with higher speeds for complicated signal processing capabilities, timing design has become critical for robust system performance, while designers are under severe cost and time-to-market pressures. In this article, we'll discuss how to use a highly-integrated programmable clock generator to address these demanding design parameters. The advantages of using these clocking solutions to reduce system cost, improve signal integrity, and reduce electromagnetic interference (EMI) through spread-spectrum clocking (SSC) will also be discussed. Finally, guidelines to overcome some basic design challenges will be presented.

Introduction

As the modern digital system migrates towards a much larger scale of integration, it usually needs half a dozen or more clock signals, running at various frequencies. Today's overall timing design usually involves accurate generation, synchronization and distribution of multiple frequencies to drive the operation of different modules such as the core processor, analog front end, i.e., audio codecs, as well as various peripherals. These numerous clocks running at much higher speeds make the noise and interference a big concern for reliable system operation. In this article, we'll discuss how a well-designed centralized clock source uses a programmable clock generator to address timing designs, while minimizing signal degradation and preventing noise interference.

Beyond system performance, factors such as faster time-to-market, lower overall cost, easier inventory management and less investment for future upgrades are major decision factors when choosing a timing solution. As a result, commodity-like design approaches are widely adopted to allow major re-use of research and development (R&D) funds, and to offer flexibility to quickly adapt to future platform changes. A programmable clock generator based on phase-locked loop (PLL) technology can boost these business competencies.

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