Using nextgen PCI Express switches to eliminate network I/O bottlenecks
(02/06/08, 03:43:00 PM EST) -- Embedded.com
Controllers in today's network-connected embedded systems often are overwhelmed by the data streaming to and from the various I/O sources; it can be difficult for the system's root complex to absorb high-speed bursty traffic such as 10Gig Ethernet when it competes with very fast streaming data from sources such as InfiniBand and Fibre Channel (FC) storage elements.
For example, when a few bytes of Ethernet data get stuck behind large packets of FC data in the root complex, the latency that is introduced by this congestion will severely impact system response time and create bandwidth limitations (see Table 1 below).

Table 1. Ethernet latency bandwidth tradeoffs
The next generation of PCI Express (PCIe) switches have added many new features to mitigate the effects of having to process competing data protocols, thereby improving overall system performance.
Advanced new features such as Read Pacing, enhanced port configuration flexibility, dynamic buffer memory allocation, and the deployment of PCIe Gen2 signaling are reducing I/O bottlenecks, providing dramatic improvements in system performance in server and storage controllers.
To read the full article, click here
Related Semiconductor IP
- UCIe Chiplet PHY & Controller
- MIPI D-PHY1.2 CSI/DSI TX and RX
- Low-Power ISP
- eMMC/SD/SDIO Combo IP
- DP/eDP
Related White Papers
- How HyperTransport and PCI Express complement each other
- Advanced switching boosts PCI Express
- Compatibility issue slows PCI Express
- With StarFabric as an on-ramp, the PCI Express Advanced Switching is ready
Latest White Papers
- Achieving Lower Power, Better Performance, And Optimized Wire Length In Advanced SoC Designs
- The pivotal role power management IP plays in chip design
- What tamper detection IP brings to SoC designs
- Analyzing Modern NVIDIA GPU cores
- RISC-V in 2025: Progress, Challenges,and What’s Next for Automotive & OpenHardware