Optimize SoC Design with a Network-on-Chip Strategy
By Andy Nightingale, Arteris
Utilizing physically aware interconnect IP from trusted third-party vendors can reduce design time and increase productivity.
Today’s system-on-chip (SoC) devices can contain hundreds of millions to over a hundred billion transistors, depending on the application. The only way to create designs of this complexity is to employ large numbers of functional blocks called intellectual-property (IP) blocks or IPs.
Many of these blocks embody well-known and standard functions, such as processor cores, communication cores (Ethernet, USB, I2C, SPI, etc.) and peripheral processes. Rather than spend valuable time and resources re-implementing these functions from scratch, SoC design teams acquire these IPs from respected third-party vendors.
Access to robust, tested, and proven IP speeds up the development process and reduces risk. Using third-party IP for common functions frees the SoC design team to focus on their own “secret sauce” IP blocks, which will differentiate their SoC from competitive offerings.
To read the full article, click here
Related Semiconductor IP
- SoC Security Platform / Hardware Root of Trust
- SPI to AHB-Lite Bridge
- Octal SPI Master/Slave Controller
- I2C and SPI Master/Slave Controller
- AHB/AXI4-Lite to AXI4-Stream Bridge
Related White Papers
- SoC design: When is a network-on-chip (NoC) not enough?
- SoC design: When a network-on-chip meets cache coherency
- A Knowledge Sharing Framework for Fabs, SoC Design Houses and IP Vendors
- VLSI Physical Design Methodology for ASIC Development with a Flavor of IP Hardening