Multi-core analysis made easy with the Nexus 5001 debug spec

In System on Chip (SoC) architectures, the ability to effectively analyze problems and optimize operations using real time in-system instrumentation is recognized as one of the most effective methods for completing product development.

Perhaps nowhere is this need more prevalent than for multi-core architectures, since this is an areas where traditional processor simulation and system analysis methodologies tend to break down when faced with issues such as concurrent programming and multiple processor flows, asynchronous operations, core-to-core integration issues, etc.

Real (either prototype or production) hardware provides the best source of information for this type of analysis, but often suffers from visibility into functionality of the system, such as processor instruction flow and data movement on embedded buses, which are not typically made available at the pin IO. Increasing the visibility of these embedded operations typically requires an instrumentation subsystem.

Debug solutions vary greatly with different IP vendors, which can make integrating debug and instrumentation systems for heterogeneous multi-core architectures difficult. In this is dynamic area, the most mature standardized solutions addressing system instrumentation and debug are those based on IEEE 5001, also widely referred to as Nexus.

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