Module Approach Ups 5 GHz WLAN Front-End Integration

Module Approach Ups 5 GHz WLAN Front-End Integration
By Boris Come and Julien Ryckaert, IMEC , CommsDesign.com
December 10, 2003 (10:11 a.m. EST)
URL: http://www.eetimes.com/story/OEG20031210S0015

Despite intense worldwide activity, 5 GHz OFDM-WLAN remains an emerging technology. And, due to its immaturity, designers have some big steps to make on the integration front.

One area where integration is most needed is in the RF front-end of a 5 GHz WLAN design. While designers have made strides toward integrating a full 802.11a radio on a single CMOS chip, designers have struggled implementing power amplifiers (PAs), RF filters, and other front-end components in the same IC. This has forced designers to rely on building 802.11a architectures using a discrete component approach.

To solve this problem, this article describes a single-package 5GHz WLAN RF module comprising a BiCMOS IC, commercial GaAs PA and TX/RX switch, high-quality integrated RF filters and a patch antenna. In this article, the complete radio link is evaluated on a demonstration platform that implements an orthogonal frequency division multiplexing (OFDM) intellectual proper ty (IP) core and mixed-signal, fast-converging interface, that control the front-end to ensure optimal reception within the limited acquisition time associated to burst-mode communication systems. Overall power consumption issues will also be discussed. To start off, however, let's look at the proposed module design.

Packing It In
For WLAN applications, integrated solutions realized in a MMIC technology have recently been demonstrated but they suffer from the high production cost of these technologies. Recent advances in modern silicon technologies allow direct-conversion and low-IF architectures to be used in radio systems. Through these RF developments, the dream of a fully integrated radio system, avoiding the expensive external SAW filters, is slowly becoming a reality. However, the road towards a system fully integrated on a single chip (SoC) still contains pitfalls in order to meet the performances expected from high-end applications such as WLAN.

The power amplifier is one componen t that makes a fully integrated SoC a challenge. The high-output powers required in a power amplifier architecture make it difficult to develop these in a generic CMOS process, thus making it tough for designers to implement this with other RF components on silicon.

PAs, however, don't cause the only headaches for designers. Other elements of the front-end, like the TX/RX switch, the RF filters, or the VCO tank, are also hard to implement in standard silicon technologies.

Due to the challenge with integrating all RF components on the same die, most 5 GHz WLAN chip vendors have shifted toward an approach where there is one main transceiver device accompanied by a host of external components. But, while good for the short-term, designers need to find an optimal way to integrate these critical external components in a single package while keeping the cost and the size of the system as low as possible.

The bottom left image of Figure 1 presents a solution for the integration of the complete system in a single package. In this example, a silicon BiCMOS chip has been assembled together with all the external components required for high performance WLAN. The external components include a GaAs power amplifier, high quality RF filters, a GaAs Tx/Rx switch and an antenna. The BiCMOS IC consists of an LNA and a PPA.

Heterogeneous systems, such as the one shown in Figure 1, together with the need for miniaturization, require packaging and integration techniques more involved than all current reported work. Fortunately, through the use of multi-chip module with thin-film dispersion (MCM-D), we can solve the problem and integrate high-quality RF filters together with a BiCMOS IC in the same module. Let's take a closer look at MCM-D and it's impact on the desi gn of 5 GHz WLAN front ends.

MCM-D: What's it All About?
MCM-D is a thin-film interconnection technology providing high-quality integrated passives, where chips can be mounted through a flip-chip technique. The MCM-D technology consists of one aluminum layer and two copper layers alternating with dielectric layers of benzocyclobutene (BCB, εr=2.7). Inductors with quality factors up to 100 at 10GHz, Ta2O5 capacitors up to 1nF and a wide range of coplanar waveguides can be realized in these layers.

The lithographic nature of MCM-D technology guarantees low tolerances due to process variations (1% on inductors and 5% on BCB capacitors). The high-quality RF filters are designed in this technology and do not require any trimming.

In the receive path, the filtering consists of a 0.8-dB loss, two-section inductor-capacitor (LC) highpass filter before the low-noise amplifier (LNA) to reject the low-frequency blockers. The receive path also requires a three-section LC bandpass filter (BPF) after the LNA that provides the required image rejection at the downconverter input in order to downconvert an IF of 900 MHz. Using the MCM-D technology, a noise figure of less than 6 dB has been measured on the complete receive chain with a rejection of 50 dB at 4.5GHz.

In the transmit chain, a similar BPF is used before the PA and a 0.8-dB loss, two-section LC lowpass filter after the PA. In this chain, the overall 1-dB compression point is higher than +23 dBm with a rejection of 30 dB at 5.8 GHz.

The MCM-D module is also used as an interconnection medium for different blocks. The GaAs switch and the BiCMOS chip are mounted on the module. The GaAs switch is a commercial component and the BiCMOS chip is designed in-house and realized in a 0.35um SiGe technology.

The MCM-D substrate carrying the BiCMOS chip is then mounted on a 0.8-mm thick BGA and connected via bondwires. A packaged GaAs PA is mounted next to the BiCMOS chip using a flip-chip technique.

A cavity is formed in the BGA to reduce the length of the bondwires to the MCM-D. Their measured insertion loss is lower than 0.4 dB at 5 GHz. The BGA technology consists of four copper metal layers and three RO4003 dielectric layers (εr =3.38). The ball connections to the PCB modify the electrical properties of the system and must be compensated for on the BGA itself. After compensation, the measured insertion loss of these balls is lower than 0.1dB at 5GHz (see Figure 1 above).

The antenna is realized on a similar laminate. This laminate is mounted as a cap on the first BGA and a 1.5-mm cavity is machined in the laminate bottom-layer to encapsulate the PA and the MCM-D module. The antenna is a square ring that provides circular polarization. The measured efficiency is better than 80% and the measured reflection coefficient is below -10 dB over the 5.15 to 5.35 GHz frequency band of the IEEE802.11a standard. The overall dimension of the module is 25 x 25 x 4.3 mm.

Interference and Compensation Techniques
End -to-end wireless links based on the proposed front-end and a standards compliant OFDM core have been evaluated with a complete digital calibration, compensation and control engine on FPGA, tightly integrated with the OFDM core modem. This building block controls the burst acquisition including AGC and DC offset removal through mixed-signal feedback loops, and, for homodyne receiver architectures, implements a digital-only I/Q mismatch estimation and compensation algorithm that exploits the specificities of the OFDM burst preambles. As a key design strategy, the building block relies on digital-only estimation to be independent from front-end implementations and shows fast convergence: estimation and compensation steps are all applied during IEEE 802.11a compliant preamble acquisition. When a signal rises from the noise floor, a discrete three-step joint algorithm adjusts the front-end gains. This and timing synchronization is performed in 8 μs during the first half of the preamble (STS).

During the se cond half of the preamble (LTS), carrier frequency offset (CFO) is estimated and compensated in the time domain (after conversion to the frequency domain the channel response is estimated). The design strategy for these algorithm (fast converging, digital only estimation) is exemplified below with the AGC implementation.

To enhance convergence time of the automatic gain control (AGC) algorithm, an AGC algorithm was developed that relies both on design-time and on run-time information. Additionally, a digital architecture is used that contains a run-time controller that handles all saturation scenarios and a configuration mapper that uses both run-time information obtained through digital estimators but also design-time information.

An extended cascade analysis at design-time provides the optimum front-end configuration for each RF input power level to the configuration mapper (Figure 2). The configuration mapper controls the variable gain amplifiers (VGAs) in the front-end. This control signa l closes a mixed-signal feedback loop. AGC becomes thus subject of both the overall impulse response of the involved analog forward and feedback paths, and the digital implementation and algorithm delays. Digital estimators provide signal power estimates during acquisition phase.

The algorithm proposed here is non-continuous in time and thus insensitive to the shape of the mixed-signal front-end impulse response. The first part of the acquisition preamble is subdivided into three phases, each consisting of an estimation and compensation phase. The configuration mapper will adapt the VGA gain at the start of each compensation phase. For the quality of the digital estimates, it is better to reduce the number of estimation samples t han to take into account samples that are affected by the gain change transients. This algorithm can be easily extended with joint estimation of the DC offsets likely present in direct-conversion architectures.

Flexible Demo Platform
A flexible robust hardware platform has been developed to shorten the development time that is needed to build a high data rate system demonstrator. This platform It allows to embed prototype analog, mixed-signal or digital ASICs and to implement algorithms on flexible hardware and software (Figure 3).

The modular, plug-in hardware boards features a flexible Virtex-II XilinX FPGA (XC2V3000/6000), high data rate serial links, flexible clock distribution network, and an industry-standard CompactPCI interface. Serving as the kernel of the board, the FPGA orchestrates all com munication links between the components on the board and between other boards or CompactPCI peripheral boards. This allows to build and to debug a board gradually.

Besides these reusable blocks, designers can implement prototype IP cores on the multi-million gates FPGA. General-purpose motherboards can also be plugged in that provides power supplies, clocks, and another smaller FPGA for control logic and mixed-signal interface implementation. This smaller FPGA cal also be used for communication through the high-speed link to the other boards.

Complete front-ends can be implemented as daughter boards. The single-package RF front-end described above is implemented on such a daughter board, whereas the mixed-signal interface also described above is implemented on FPGA.

An access point and a terminal were implemented on two such platforms in order to validate the IP cores discussed here and perform system measurements. This implementation is compliant with error-vector-magnitude (EVM) and filter m ask specifications in the IEEE 802.11a standard. Burst preambles, which are used during to perform acquisition and calibration of the front-end, are also taken from this IEEE standard. The protocol layer, however, is similar to the one defined in the ETSI HiperLAN/2 standard to deliver quality of service (QoS) capabilities.

Reducing Power Consumption
All WLAN chipsets reported in literature are based either on super-heterodyne or on direct-conversion architectures, and at least external antenna and antenna switch, most often combined with an off-chip LNA and PA in GaAs technology. These systems show similar performances, as compliancy with the 802.11a standard is mandatory, which is sufficient for most current applications. However, there is still a drastic need for improvement when one looks at implementation of such WLAN systems into handheld device: the power consumption such OFDM-based systems will limit the battery life-time to a couple of hours.

This issue is not PA-only related: as suming:

• for a transmitter physical layer, 100 mW power consumption for the digital PHY, and 250mW for the mixed-signal front-end (digital interface, ADCs and LO generation included)
• assuming a Class-A amplifier with back-off with intrinsic efficiency of 10% compared to a Doherty amplifier with back-off with intrinsic efficiency of 30%
• the overall transmitter PHY efficiency for +16-dBm average output power increases only from 5 to 8% when using the Doherty amplifier

It is only when considering much higher output powers that implementing complex PA architectures pays off (Figure 4). For example, at +23-dBm average output powers, the transmitter PHY efficiency is 20% with the Doherty PA compared to 8% for the Class-A PA. Another efficient technique to increase power efficiency is to reduce the back-off at which the PA can operate while maintaining low in-band and out-of-band distortion. RF feedback or digital predistortion are such candidates.

Unlike predistortion, RF feedback is a local linearization technique and does not require a calibration phase. RF feedback operates at runtime the way it has been implemented at design time, with very little tuning possibilities. As a result, accurate and extensive knowledge on the RF power module behavior is mandatory. It can be acquired either from an extensive measurement campaign and a significant modeling effort (under the all parameter variations, like operating frequency, temperature, voltage supply, bias supply, input power, input energy's history, heat sink properties, etc.), or directly from a transistor level schematic plus mechanical environment model of the power module.

Digital predistortion is preferred because for its flexibility, as accurate circuit knowledge of the PA module (which is usually not available to t he designer using commercial components) is not required for the implementation. A behavioral model is sufficient to implement the algorithm that will extract the predistortion coefficient at run-time during a calibration phase. Digital predistortion applied to Class-A PAs can reduce the required back-off from 10 dB to close to 3 dB, increasing the PA intrinsic power efficiency from about 10% to close to 20%.

These two methods are direct extensions to the presented work. Predistortion will be included in the mixed-signal interface at the transmit side. Additionally, the Doherty amplifier implemented, following our SiP approach and based on GaAs transistors and interconnect on the MCM-D, will deliver burst average output powers up to +23 dBm.

Wrap Up
With increasing focus in integrating more WLAN flavors on a single CMOS chip (802.11a, b, g, and more), the number of external RF components around the chip is exploding. Advanced packaging techniques will help, as illustrated here with a 5GH z WLAN transceiver with no external RF components nor connector: the antenna, active GaAs circuits and other high-quality passives are integrated in the package with the transceiver ASIC. IMEC also advocates intensive use of digital compensation techniques, tightly integrated around the OFDM digital core and without modification of the OFDM frame format, to enhance the link performances. These points are key factors for reduced bill of materials and time-to-market in final product implementations: integrate the RF chip in an advanced package, integrate the package in a system.

About the Authors
Boris Come is a senior researcher at IMEC. He graduated from the National Engineering School of Electronics in Toulouse, ENSEEIHT and can be reached at comeb@imec.be.

Julien Ryckaert is a researcher at IMEC. He received his B.Eng. degree from the University of Brussels annd can be reached at ryckj@imec.be