High-Speed Board Layout Challenges in FPGA/SDI Sub-Systems
By Tsun-Kit Chin, National Semiconductor Corp.
pldesignline.com (November 18, 2009)
Introduction
Television and cinema have entered the digital age. Video pictures are used to transport at standard definition rate (270 Mb/s), upgraded to high definition rate (1.485 Gb/s), and are now migrating to 3 Gb/s. The migration to higher speeds enables higher resolution images for entertainment, but it also presents challenges to hardware engineers and physical layout designers. Many video systems are implemented with feature-rich FPGA and multi-rate SDI integrated circuits that support high performance professional video transport over long distances. FPGAs demand high density routing with fine trace width while high-speed analog SDI routing demands impedance matching and signal fidelity. This paper outlines the layout challenges facing hardware engineers and provides recommendations for dealing with these challenges.
To read the full article, click here
Related Semiconductor IP
- Xtal Oscillator on TSMC CLN7FF
- Wide Range Programmable Integer PLL on UMC L65LL
- Wide Range Programmable Integer PLL on UMC L130EHS
- Wide Range Programmable Integer PLL on TSMC CLN90G-GT-LP
- Wide Range Programmable Integer PLL on TSMC CLN80GC
Related White Papers
- Consumer IC Advances -> Set- top box SoC ready for high-speed demands
- IC Physical Design: Portable Layout and Simulation Technigues for ADSL Analog Devices
- Chip, board designers differ on preferences, concerns
- Layout compaction accelerates SoC design through hard IP reuse